Changes in kernel/arch/sparc64/src/mm/sun4u/as.c [74cbac7d:da1bafb] in mainline
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kernel/arch/sparc64/src/mm/sun4u/as.c
r74cbac7d rda1bafb 41 41 42 42 #ifdef CONFIG_TSB 43 43 44 #include <arch/mm/tsb.h> 44 45 #include <arch/memstr.h> … … 47 48 #include <bitops.h> 48 49 #include <macros.h> 50 49 51 #endif /* CONFIG_TSB */ 50 52 … … 58 60 } 59 61 60 int as_constructor_arch(as_t *as, int flags)62 int as_constructor_arch(as_t *as, unsigned int flags) 61 63 { 62 64 #ifdef CONFIG_TSB … … 64 66 * The order must be calculated with respect to the emulated 65 67 * 16K page size. 66 */ 67 int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * 68 * 69 */ 70 uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * 68 71 sizeof(tsb_entry_t)) >> FRAME_WIDTH); 69 72 70 73 uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); 71 74 72 75 if (!tsb) 73 76 return -1; 74 77 75 78 as->arch.itsb = (tsb_entry_t *) tsb; 76 79 as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * 77 80 sizeof(tsb_entry_t)); 78 81 79 82 memsetb(as->arch.itsb, 80 83 (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); 81 84 #endif 85 82 86 return 0; 83 87 } … … 93 97 sizeof(tsb_entry_t)) >> FRAME_WIDTH; 94 98 frame_free(KA2PA((uintptr_t) as->arch.itsb)); 99 95 100 return cnt; 96 101 #else … … 99 104 } 100 105 101 int as_create_arch(as_t *as, int flags)106 int as_create_arch(as_t *as, unsigned int flags) 102 107 { 103 108 #ifdef CONFIG_TSB 104 109 tsb_invalidate(as, 0, (size_t) -1); 105 110 #endif 111 106 112 return 0; 107 113 } … … 123 129 * 124 130 * Moreover, the as->asid is protected by asidlock, which is being held. 131 * 125 132 */ 126 133 … … 130 137 * secondary context register from the TL=1 code just before switch to 131 138 * userspace. 139 * 132 140 */ 133 141 ctx.v = 0; 134 142 ctx.context = as->asid; 135 143 mmu_secondary_context_write(ctx.v); 136 137 #ifdef CONFIG_TSB 144 145 #ifdef CONFIG_TSB 138 146 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); 139 147 140 148 ASSERT(as->arch.itsb && as->arch.dtsb); 141 149 142 150 uintptr_t tsb = (uintptr_t) as->arch.itsb; 143 151 144 152 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { 145 153 /* … … 147 155 * by the locked 4M kernel DTLB entry. We need 148 156 * to map both TSBs explicitly. 157 * 149 158 */ 150 159 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); 151 160 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); 152 161 } 153 162 154 163 /* 155 164 * Setup TSB Base registers. 165 * 156 166 */ 157 167 tsb_base_reg_t tsb_base; 158 168 159 169 tsb_base.value = 0; 160 170 tsb_base.size = TSB_SIZE; 161 171 tsb_base.split = 0; 162 172 163 173 tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; 164 174 itsb_base_write(tsb_base.value); … … 175 185 * Clearing the extension registers will ensure that the value of the 176 186 * TSB Base register will be used as an address of TSB, making the code 177 * compatible with the US port. 187 * compatible with the US port. 188 * 178 189 */ 179 190 itsb_primary_extension_write(0); … … 195 206 void as_deinstall_arch(as_t *as) 196 207 { 197 198 208 /* 199 209 * Note that we don't and may not lock the address space. That's ok … … 201 211 * 202 212 * Moreover, the as->asid is protected by asidlock, which is being held. 203 */ 204 213 * 214 */ 215 205 216 #ifdef CONFIG_TSB 206 217 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); 207 218 208 219 ASSERT(as->arch.itsb && as->arch.dtsb); 209 220 210 221 uintptr_t tsb = (uintptr_t) as->arch.itsb; 211 222 212 223 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { 213 224 /*
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