Changeset dbb6886 in mainline


Ignore:
Timestamp:
2005-12-13T22:53:26Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8ad925c
Parents:
91ef0d95
Message:

sparc64 work.
Support for TLB Demap operations.
Add tlb_invalidate(), tlb_invalidate_asid() and tlb_invalidate_page() (latter two are broken as they ignore asid).

Location:
arch/sparc64
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • arch/sparc64/include/mm/asid.h

    r91ef0d95 rdbb6886  
    3030#define __sparc64_ASID_H__
    3131
    32 typedef int asid_t;
     32#include <arch/types.h>
     33
     34/*
     35 * On SPARC, Context means the same thing as ASID trough out the kernel.
     36 */
     37typedef __u16 asid_t;
    3338
    3439#define asid_get()      0
  • arch/sparc64/include/mm/page.h

    r91ef0d95 rdbb6886  
    6767#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)
    6868
     69union page_address {
     70        __address address;
     71        struct {
     72                __u64 vpn : 51;         /**< Virtual Page Number. */
     73                unsigned offset : 13;   /**< Offset. */
     74        } __attribute__ ((packed));
     75};
     76
     77typedef union page_address page_address_t;
     78
    6979extern void page_arch_init(void);
    7080
  • arch/sparc64/include/mm/tlb.h

    r91ef0d95 rdbb6886  
    3131
    3232#include <arch/mm/tte.h>
     33#include <arch/mm/page.h>
    3334#include <arch/asm.h>
    3435#include <arch/barrier.h>
     
    9495        __u64 value;
    9596        struct {
    96                 __u64 va : 51;          /**< Virtual Address. */
     97                __u64 vpn : 51;         /**< Virtual Address bits 63:13. */
    9798                unsigned context : 13;  /**< Context identifier. */
    9899        } __attribute__ ((packed));
     
    101102typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
    102103
     104/** TLB Demap Operation types. */
     105#define TLB_DEMAP_PAGE          0
     106#define TLB_DEMAP_CONTEXT       1
     107
     108/** TLB Demap Operation Context register encodings. */
     109#define TLB_DEMAP_PRIMARY       0
     110#define TLB_DEMAP_SECONDARY     1
     111#define TLB_DEMAP_NUCLEUS       2
     112
     113/** TLB Demap Operation Address. */
     114union tlb_demap_addr {
     115        __u64 value;
     116        struct {
     117                __u64 vpn: 51;          /**< Virtual Address bits 63:13. */
     118                unsigned : 6;           /**< Ignored. */
     119                unsigned type : 1;      /**< The type of demap operation. */
     120                unsigned context : 2;   /**< Context register selection. */
     121                unsigned : 4;           /**< Zero. */
     122        } __attribute__ ((packed));
     123};
     124typedef union tlb_demap_addr tlb_demap_addr_t;
     125
    103126/** Read IMMU TLB Data Access Register.
    104127 *
     
    116139}
    117140
     141/** Write IMMU TLB Data Access Register.
     142 *
     143 * @param entry TLB Entry index.
     144 * @param value Value to be written.
     145 */
     146static inline __u64 itlb_data_access_write(index_t entry, __u64 value)
     147{
     148        tlb_data_access_addr_t reg;
     149       
     150        reg.value = 0;
     151        reg.tlb_entry = entry;
     152        asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
     153        flush();
     154}
     155
    118156/** Read DMMU TLB Data Access Register.
    119157 *
     
    131169}
    132170
     171/** Write DMMU TLB Data Access Register.
     172 *
     173 * @param entry TLB Entry index.
     174 * @param value Value to be written.
     175 */
     176static inline __u64 dtlb_data_access_write(index_t entry, __u64 value)
     177{
     178        tlb_data_access_addr_t reg;
     179       
     180        reg.value = 0;
     181        reg.tlb_entry = entry;
     182        asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
     183        flush();
     184}
     185
    133186/** Read IMMU TLB Tag Read Register.
    134187 *
     
    201254}
    202255
     256/** Perform IMMU TLB Demap Operation.
     257 *
     258 * @param type Selects between context and page demap.
     259 * @param context_encoding Specifies which Context register has Context ID for demap.
     260 * @param page Address which is on the page to be demapped.
     261 */
     262static inline void itlb_demap(int type, int context_encoding, __address page)
     263{
     264        tlb_demap_addr_t da;
     265        page_address_t pg;
     266       
     267        da.value = 0;
     268        pg.address = page;
     269       
     270        da.type = type;
     271        da.context = context_encoding;
     272        da.vpn = pg.vpn;
     273       
     274        asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
     275        flush();
     276}
     277
     278/** Perform DMMU TLB Demap Operation.
     279 *
     280 * @param type Selects between context and page demap.
     281 * @param context_encoding Specifies which Context register has Context ID for demap.
     282 * @param page Address which is on the page to be demapped.
     283 */
     284static inline void dtlb_demap(int type, int context_encoding, __address page)
     285{
     286        tlb_demap_addr_t da;
     287        page_address_t pg;
     288       
     289        da.value = 0;
     290        pg.address = page;
     291       
     292        da.type = type;
     293        da.context = context_encoding;
     294        da.vpn = pg.vpn;
     295       
     296        asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
     297        flush();
     298}
     299
    203300#endif
  • arch/sparc64/include/mm/tte.h

    r91ef0d95 rdbb6886  
    5656                unsigned soft2 : 9;     /**< Software defined field. */
    5757                unsigned diag : 9;      /**< Diagnostic data. */
    58                 unsigned pa : 28;       /**< Physical page number. */
     58                unsigned pfn : 28;      /**< Physical Address bits, bits 40:13. */
    5959                unsigned soft : 6;      /**< Software defined field. */
    6060                unsigned l : 1;         /**< Lock. */
  • arch/sparc64/src/mm/tlb.c

    r91ef0d95 rdbb6886  
    3030#include <mm/tlb.h>
    3131#include <print.h>
     32#include <arch/types.h>
     33#include <typedefs.h>
    3234
    3335void tlb_arch_init(void)
     
    4749                t.value = itlb_tag_read_read(i);
    4850               
    49                 printf("%d: va=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
    50                         i, t.va, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pa, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
     51                printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
     52                        i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    5153        }
    5254
     
    5658                t.value = dtlb_tag_read_read(i);
    5759               
    58                 printf("%d: va=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
    59                         i, t.va, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pa, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
     60                printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
     61                        i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    6062        }
    6163
    6264}
     65
     66/** Invalidate all unlocked ITLB and DTLB entries. */
     67void tlb_invalidate_all(void)
     68{
     69        int i;
     70        tlb_data_t d;
     71        tlb_tag_read_reg_t t;
     72
     73        for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
     74                d.value = itlb_data_access_read(i);
     75                if (!d.l) {
     76                        printf("invalidating ");
     77                        t.value = itlb_tag_read_read(i);
     78                        d.v = false;
     79                        itlb_tag_access_write(t.value);
     80                        itlb_data_access_write(i, d.value);
     81                }
     82        }
     83       
     84        for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
     85                d.value = dtlb_data_access_read(i);
     86                if (!d.l) {
     87                        t.value = dtlb_tag_read_read(i);
     88                        d.v = false;
     89                        dtlb_tag_access_write(t.value);
     90                        dtlb_data_access_write(i, d.value);
     91                }
     92        }
     93       
     94}
     95
     96/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
     97 *
     98 * @param asid Address Space ID.
     99 */
     100void tlb_invalidate_asid(asid_t asid)
     101{
     102        /* TODO: write asid to some Context register and encode the register in second parameter below. */
     103        itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
     104        dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
     105}
     106
     107/** Invalidate all ITLB and DLTB entries for specified page in specified address space.
     108 *
     109 * @param asid Address Space ID.
     110 * @param page Page which to sweep out from ITLB and DTLB.
     111 */
     112void tlb_invalidate_page(asid_t asid, __address page)
     113{
     114        /* TODO: write asid to some Context register and encode the register in second parameter below. */
     115        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page);
     116        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page);
     117}
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