Changes in kernel/arch/ia64/include/asm.h [7a0359b:dbd5df1b] in mainline
- File:
-
- 1 edited
-
kernel/arch/ia64/include/asm.h (modified) (27 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia64/include/asm.h
r7a0359b rdbd5df1b 40 40 #include <typedefs.h> 41 41 #include <arch/register.h> 42 #include <trace.h>43 42 44 43 #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL 45 44 46 NO_TRACEstatic inline void pio_write_8(ioport8_t *port, uint8_t v)45 static inline void pio_write_8(ioport8_t *port, uint8_t v) 47 46 { 48 47 uintptr_t prt = (uintptr_t) port; … … 57 56 } 58 57 59 NO_TRACEstatic inline void pio_write_16(ioport16_t *port, uint16_t v)58 static inline void pio_write_16(ioport16_t *port, uint16_t v) 60 59 { 61 60 uintptr_t prt = (uintptr_t) port; … … 70 69 } 71 70 72 NO_TRACEstatic inline void pio_write_32(ioport32_t *port, uint32_t v)71 static inline void pio_write_32(ioport32_t *port, uint32_t v) 73 72 { 74 73 uintptr_t prt = (uintptr_t) port; … … 83 82 } 84 83 85 NO_TRACEstatic inline uint8_t pio_read_8(ioport8_t *port)84 static inline uint8_t pio_read_8(ioport8_t *port) 86 85 { 87 86 uintptr_t prt = (uintptr_t) port; … … 96 95 } 97 96 98 NO_TRACEstatic inline uint16_t pio_read_16(ioport16_t *port)97 static inline uint16_t pio_read_16(ioport16_t *port) 99 98 { 100 99 uintptr_t prt = (uintptr_t) port; … … 109 108 } 110 109 111 NO_TRACEstatic inline uint32_t pio_read_32(ioport32_t *port)110 static inline uint32_t pio_read_32(ioport32_t *port) 112 111 { 113 112 uintptr_t prt = (uintptr_t) port; … … 127 126 * The stack is assumed to be STACK_SIZE long. 128 127 * The stack must start on page boundary. 129 * 130 */ 131 NO_TRACE static inline uintptr_t get_stack_base(void) 132 { 133 uint64_t v; 134 135 /* 136 * I'm not sure why but this code inlines badly 137 * in scheduler, resulting in THE shifting about 138 * 16B and causing kernel panic. 139 * 140 * asm volatile ( 141 * "and %[value] = %[mask], r12" 142 * : [value] "=r" (v) 143 * : [mask] "r" (~(STACK_SIZE - 1)) 144 * ); 145 * return v; 146 * 147 * The following code has the same semantics but 148 * inlines correctly. 149 * 150 */ 128 */ 129 static inline uintptr_t get_stack_base(void) 130 { 131 uint64_t v; 132 133 /* I'm not sure why but this code bad inlines in scheduler, 134 so THE shifts about 16B and causes kernel panic 135 136 asm volatile ( 137 "and %[value] = %[mask], r12" 138 : [value] "=r" (v) 139 : [mask] "r" (~(STACK_SIZE - 1)) 140 ); 141 return v; 142 143 This code have the same meaning but inlines well. 144 */ 151 145 152 146 asm volatile ( … … 161 155 * 162 156 * @return PSR. 163 * 164 */ 165 NO_TRACE static inline uint64_t psr_read(void) 157 */ 158 static inline uint64_t psr_read(void) 166 159 { 167 160 uint64_t v; … … 178 171 * 179 172 * @return Return location of interruption vector table. 180 * 181 */ 182 NO_TRACE static inline uint64_t iva_read(void) 173 */ 174 static inline uint64_t iva_read(void) 183 175 { 184 176 uint64_t v; … … 195 187 * 196 188 * @param v New location of interruption vector table. 197 * 198 */ 199 NO_TRACE static inline void iva_write(uint64_t v) 189 */ 190 static inline void iva_write(uint64_t v) 200 191 { 201 192 asm volatile ( … … 205 196 } 206 197 198 207 199 /** Read IVR (External Interrupt Vector Register). 208 200 * 209 * @return Highest priority, pending, unmasked external 210 * interrupt vector. 211 * 212 */ 213 NO_TRACE static inline uint64_t ivr_read(void) 201 * @return Highest priority, pending, unmasked external interrupt vector. 202 */ 203 static inline uint64_t ivr_read(void) 214 204 { 215 205 uint64_t v; … … 223 213 } 224 214 225 NO_TRACEstatic inline uint64_t cr64_read(void)215 static inline uint64_t cr64_read(void) 226 216 { 227 217 uint64_t v; … … 235 225 } 236 226 227 237 228 /** Write ITC (Interval Timer Counter) register. 238 229 * 239 230 * @param v New counter value. 240 * 241 */ 242 NO_TRACE static inline void itc_write(uint64_t v) 231 */ 232 static inline void itc_write(uint64_t v) 243 233 { 244 234 asm volatile ( … … 251 241 * 252 242 * @return Current counter value. 253 * 254 */ 255 NO_TRACE static inline uint64_t itc_read(void) 243 */ 244 static inline uint64_t itc_read(void) 256 245 { 257 246 uint64_t v; … … 268 257 * 269 258 * @param v New match value. 270 * 271 */ 272 NO_TRACE static inline void itm_write(uint64_t v) 259 */ 260 static inline void itm_write(uint64_t v) 273 261 { 274 262 asm volatile ( … … 281 269 * 282 270 * @return Match value. 283 * 284 */ 285 NO_TRACE static inline uint64_t itm_read(void) 271 */ 272 static inline uint64_t itm_read(void) 286 273 { 287 274 uint64_t v; … … 298 285 * 299 286 * @return Current vector and mask bit. 300 * 301 */ 302 NO_TRACE static inline uint64_t itv_read(void) 287 */ 288 static inline uint64_t itv_read(void) 303 289 { 304 290 uint64_t v; … … 315 301 * 316 302 * @param v New vector and mask bit. 317 * 318 */ 319 NO_TRACE static inline void itv_write(uint64_t v) 303 */ 304 static inline void itv_write(uint64_t v) 320 305 { 321 306 asm volatile ( … … 328 313 * 329 314 * @param v This value is ignored. 330 * 331 */ 332 NO_TRACE static inline void eoi_write(uint64_t v) 315 */ 316 static inline void eoi_write(uint64_t v) 333 317 { 334 318 asm volatile ( … … 341 325 * 342 326 * @return Current value of TPR. 343 * 344 */ 345 NO_TRACE static inline uint64_t tpr_read(void) 327 */ 328 static inline uint64_t tpr_read(void) 346 329 { 347 330 uint64_t v; … … 358 341 * 359 342 * @param v New value of TPR. 360 * 361 */ 362 NO_TRACE static inline void tpr_write(uint64_t v) 343 */ 344 static inline void tpr_write(uint64_t v) 363 345 { 364 346 asm volatile ( … … 374 356 * 375 357 * @return Old interrupt priority level. 376 * 377 */ 378 NO_TRACE static ipl_t interrupts_disable(void) 358 */ 359 static ipl_t interrupts_disable(void) 379 360 { 380 361 uint64_t v; … … 396 377 * 397 378 * @return Old interrupt priority level. 398 * 399 */ 400 NO_TRACE static ipl_t interrupts_enable(void) 379 */ 380 static ipl_t interrupts_enable(void) 401 381 { 402 382 uint64_t v; … … 419 399 * 420 400 * @param ipl Saved interrupt priority level. 421 * 422 */ 423 NO_TRACE static inline void interrupts_restore(ipl_t ipl) 401 */ 402 static inline void interrupts_restore(ipl_t ipl) 424 403 { 425 404 if (ipl & PSR_I_MASK) … … 432 411 * 433 412 * @return PSR. 434 * 435 */ 436 NO_TRACE static inline ipl_t interrupts_read(void) 413 */ 414 static inline ipl_t interrupts_read(void) 437 415 { 438 416 return (ipl_t) psr_read(); … … 444 422 * 445 423 */ 446 NO_TRACEstatic inline bool interrupts_disabled(void)424 static inline bool interrupts_disabled(void) 447 425 { 448 426 return !(psr_read() & PSR_I_MASK); … … 450 428 451 429 /** Disable protection key checking. */ 452 NO_TRACEstatic inline void pk_disable(void)430 static inline void pk_disable(void) 453 431 { 454 432 asm volatile (
Note:
See TracChangeset
for help on using the changeset viewer.
