Changeset dd14cced in mainline
- Timestamp:
- 2005-12-11T14:35:56Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 54aff98
- Parents:
- a98d2ec
- Location:
- arch/mips32
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips32/include/mm/tlb.h
ra98d2ec rdd14cced 133 133 } 134 134 135 #define tlb_invalidate(asid) tlb_invalidate_asid(asid) 136 135 137 extern void tlb_invalid(struct exception_regdump *pstate); 136 138 extern void tlb_refill(struct exception_regdump *pstate); -
arch/mips32/src/mm/tlb.c
ra98d2ec rdd14cced 56 56 void tlb_arch_init(void) 57 57 { 58 int i; 59 58 60 cp0_pagemask_write(TLB_PAGE_MASK_16K); 59 60 tlb_invalidate_all(); 61 cp0_entry_hi_write(0); 62 cp0_entry_lo0_write(0); 63 cp0_entry_lo1_write(0); 64 65 /* Clear and initialize TLB. */ 66 67 for (i = 0; i < TLB_ENTRY_COUNT; i++) { 68 cp0_index_write(i); 69 tlbwi(); 70 } 61 71 62 72 /* … … 294 304 symbol = s; 295 305 panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol); 296 }297 298 /** Invalidate TLB entries with specified ASID299 *300 * Invalidate TLB entries with specified ASID.301 *302 * @param asid ASID.303 */304 void tlb_invalidate(asid_t asid)305 {306 entry_hi_t hi;307 ipl_t ipl;308 int i;309 310 ASSERT(asid != ASID_INVALID);311 312 ipl = interrupts_disable();313 314 for (i = 0; i < TLB_ENTRY_COUNT; i++) {315 cp0_index_write(i);316 tlbr();317 318 hi.value = cp0_entry_hi_read();319 if (hi.asid == asid) {320 cp0_pagemask_write(TLB_PAGE_MASK_16K);321 cp0_entry_hi_write(0);322 cp0_entry_lo0_write(0);323 cp0_entry_lo1_write(0);324 tlbwi();325 }326 }327 328 interrupts_restore(ipl);329 306 } 330 307 … … 415 392 void tlb_invalidate_all(void) 416 393 { 394 ipl_t ipl; 395 entry_lo_t lo0, lo1; 417 396 int i; 418 397 419 cp0_entry_hi_write(0); 420 cp0_entry_lo0_write(0); 421 cp0_entry_lo1_write(0); 398 ipl = interrupts_disable(); 422 399 423 400 for (i = 0; i < TLB_ENTRY_COUNT; i++) { 424 401 cp0_index_write(i); 402 tlbr(); 403 404 lo0.value = cp0_entry_lo0_read(); 405 lo1.value = cp0_entry_lo1_read(); 406 407 lo0.v = 0; 408 lo1.v = 0; 409 410 cp0_entry_lo0_write(lo0.value); 411 cp0_entry_lo1_write(lo1.value); 412 425 413 tlbwi(); 426 414 } 415 416 interrupts_restore(ipl); 427 417 } 428 418 … … 433 423 void tlb_invalidate_asid(asid_t asid) 434 424 { 425 ipl_t ipl; 426 entry_lo_t lo0, lo1; 435 427 entry_hi_t hi; 436 428 int i; 437 429 430 ASSERT(asid != ASID_INVALID); 431 432 ipl = interrupts_disable(); 433 438 434 for (i = 0; i < TLB_ENTRY_COUNT; i++) { 439 435 cp0_index_write(i); 440 436 tlbr(); 441 437 438 hi.value = cp0_entry_hi_read(); 439 442 440 if (hi.asid == asid) { 443 cp0_entry_lo0_write(0); 444 cp0_entry_lo1_write(0); 441 lo0.value = cp0_entry_lo0_read(); 442 lo1.value = cp0_entry_lo1_read(); 443 444 lo0.v = 0; 445 lo1.v = 0; 446 447 cp0_entry_lo0_write(lo0.value); 448 cp0_entry_lo1_write(lo1.value); 449 445 450 tlbwi(); 446 451 } 447 452 } 448 453 454 interrupts_restore(ipl); 449 455 } 450 456 … … 456 462 void tlb_invalidate_page(asid_t asid, __address page) 457 463 { 464 ipl_t ipl; 465 entry_lo_t lo0, lo1; 458 466 entry_hi_t hi; 459 467 tlb_index_t index; 460 int i; 468 469 ASSERT(asid != ASID_INVALID); 470 471 ipl = interrupts_disable(); 461 472 462 473 hi.value = 0; 463 474 prepare_entry_hi(&hi, asid, page); 464 475 cp0_entry_hi_write(hi.value); 476 465 477 tlbp(); 466 478 index.value = cp0_index_read(); … … 468 480 if (!index.p) { 469 481 /* Entry was found, index register contains valid index. */ 470 cp0_entry_lo0_write(0); 471 cp0_entry_lo1_write(0); 482 tlbr(); 483 484 lo0.value = cp0_entry_lo0_read(); 485 lo1.value = cp0_entry_lo1_read(); 486 487 lo0.v = 0; 488 lo1.v = 0; 489 490 cp0_entry_lo0_write(lo0.value); 491 cp0_entry_lo1_write(lo1.value); 492 472 493 tlbwi(); 473 494 } 474 } 495 496 interrupts_restore(ipl); 497 }
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