Changeset dd28c1a in mainline
- Timestamp:
- 2011-12-09T17:01:16Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 979c5729
- Parents:
- 78aa0ab
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/char/i8042/i8042.c
r78aa0ab rdd28c1a 102 102 static i8042_dev_t device; 103 103 104 static void wait_ready(void) 105 { 106 while (pio_read_8(&device.regs->status) & i8042_INPUT_FULL); 104 static void wait_ready(i8042_dev_t *dev) 105 { 106 assert(dev); 107 while (pio_read_8(&dev->regs->status) & i8042_INPUT_FULL); 107 108 } 108 109 … … 110 111 static void i8042_connection(ipc_callid_t iid, ipc_call_t *icall, void *arg); 111 112 static int i8042_init(i8042_dev_t *dev); 112 static void i8042_port_write(i nt devid, uint8_t data);113 static void i8042_port_write(i8042_dev_t *dev, int devid, uint8_t data); 113 114 114 115 … … 179 180 180 181 /* Disable kbd and aux */ 181 wait_ready( );182 wait_ready(dev); 182 183 pio_write_8(&dev->regs->status, i8042_CMD_WRITE_CMDB); 183 wait_ready( );184 wait_ready(dev); 184 185 pio_write_8(&dev->regs->data, i8042_KBD_DISABLE | i8042_AUX_DISABLE); 185 186 … … 195 196 NAME, inr_a, inr_b); 196 197 197 wait_ready( );198 wait_ready(dev); 198 199 pio_write_8(&dev->regs->status, i8042_CMD_WRITE_CMDB); 199 wait_ready( );200 wait_ready(dev); 200 201 pio_write_8(&dev->regs->data, i8042_KBD_IE | i8042_KBD_TRANSLATE | 201 202 i8042_AUX_IE); … … 259 260 printf(NAME ": write %" PRIun " to devid %d\n", 260 261 IPC_GET_ARG1(call), dev_id); 261 i8042_port_write( dev_id, IPC_GET_ARG1(call));262 i8042_port_write(&device, dev_id, IPC_GET_ARG1(call)); 262 263 retval = 0; 263 264 break; … … 272 273 } 273 274 274 void i8042_port_write(int devid, uint8_t data) 275 { 275 void i8042_port_write(i8042_dev_t *dev, int devid, uint8_t data) 276 { 277 assert(dev); 276 278 if (devid == DEVID_AUX) { 277 wait_ready( );278 pio_write_8(&dev ice.regs->status, i8042_CMD_WRITE_AUX);279 } 280 wait_ready( );281 pio_write_8(&dev ice.regs->data, data);279 wait_ready(dev); 280 pio_write_8(&dev->regs->status, i8042_CMD_WRITE_AUX); 281 } 282 wait_ready(dev); 283 pio_write_8(&dev->regs->data, data); 282 284 } 283 285
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