Changeset dd4d6b0 in mainline
- Timestamp:
- 2006-02-06T23:47:47Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 37b451f7
- Parents:
- 40ca402
- Location:
- arch/amd64
- Files:
-
- 2 added
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/Makefile.inc
r40ca402 rdd4d6b0 100 100 arch/$(ARCH)/src/cpu/cpu.c \ 101 101 arch/$(ARCH)/src/proc/scheduler.c \ 102 arch/$(ARCH)/src/userspace.c 102 arch/$(ARCH)/src/userspace.c \ 103 arch/$(ARCH)/src/syscall.c 103 104 104 105 ifeq ($(CONFIG_SMP),y) -
arch/amd64/include/asm.h
r40ca402 rdd4d6b0 189 189 } 190 190 191 /** Write to MSR */ 192 static inline void write_msr(__u32 msr, __u64 value) 193 { 194 __asm__ volatile ( 195 "wrmsr;" : : "c" (msr), 196 "a" ((__u32)(value)), 197 "d" ((__u32)(value >> 32)) 198 ); 199 } 200 201 static inline __native read_msr(__u32 msr) 202 { 203 __u32 ax, dx; 204 205 __asm__ volatile ( 206 "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) 207 ); 208 return ((__u64)dx << 32) | ax; 209 } 210 191 211 192 212 /** Enable local APIC -
arch/amd64/include/cpu.h
r40ca402 rdd4d6b0 38 38 #define AMD_NXE_FLAG 11 39 39 40 /* MSR registers */ 41 #define AMD_MSR_STAR 0xc0000081 42 #define AMD_MSR_LSTAR 0xc0000082 43 #define AMD_MSR_SFMASK 0xc0000084 44 40 45 #ifndef __ASM__ 41 46 -
arch/amd64/include/pm.h
r40ca402 rdd4d6b0 40 40 41 41 #define NULL_DES 0 42 /* Warning: Do not reorder next items, unless you look into syscall.c!!! */ 42 43 #define KTEXT_DES 1 43 44 #define KDATA_DES 2 44 #define U TEXT_DES 345 #define U DATA_DES 445 #define UDATA_DES 3 46 #define UTEXT_DES 4 46 47 #define KTEXT32_DES 5 48 /* EndOfWarning */ 47 49 #define TSS_DES 6 48 50 -
arch/amd64/src/amd64.c
r40ca402 rdd4d6b0 46 46 #include <panic.h> 47 47 #include <interrupt.h> 48 #include <arch/syscall.h> 48 49 49 50 /** Disable I/O on non-privileged levels … … 100 101 /* Enable No-execute pages */ 101 102 set_efer_flag(AMD_NXE_FLAG); 102 /* Enable SYSCALL/SYSRET */103 set_efer_flag(AMD_SCE_FLAG);104 103 /* Enable FPU */ 105 104 cpu_setup_fpu(); 105 106 106 /* Initialize segmentation */ 107 107 pm_init(); … … 113 113 /* Disable alignment check */ 114 114 clean_AM_flag(); 115 116 115 117 116 if (config.cpu_active == 1) { … … 133 132 ega_init(); /* video */ 134 133 } 134 /* Setup fast SYSCALL/SYSRET */ 135 syscall_setup_cpu(); 136 135 137 } 136 138 -
arch/amd64/src/asm_utils.S
r40ca402 rdd4d6b0 39 39 .text 40 40 .global interrupt_handlers 41 .global syscall_entry 41 42 .global panic_printf 42 43 … … 189 190 handler 0 IDT_ITEMS 190 191 h_end: 191 192 193 194 syscall_entry: 195 # TODO: Switch to kernel stack 196 call syscall_handler 197 # Switch back 198 sysret 199 192 200 .data 193 201 .global interrupt_handler_size -
arch/amd64/src/pm.c
r40ca402 rdd4d6b0 72 72 .granularity = 1, 73 73 .base_24_31 = 0 }, 74 /* UDATA descriptor */ 75 { .limit_0_15 = 0xffff, 76 .base_0_15 = 0, 77 .base_16_23 = 0, 78 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 79 .limit_16_19 = 0xf, 80 .available = 0, 81 .longmode = 0, 82 .special = 1, 83 .granularity = 1, 84 .base_24_31 = 0 }, 74 85 /* UTEXT descriptor */ 75 86 { .limit_0_15 = 0xffff, … … 81 92 .longmode = 1, 82 93 .special = 0, 83 .granularity = 1,84 .base_24_31 = 0 },85 /* UDATA descriptor */86 { .limit_0_15 = 0xffff,87 .base_0_15 = 0,88 .base_16_23 = 0,89 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,90 .limit_16_19 = 0xf,91 .available = 0,92 .longmode = 0,93 .special = 1,94 94 .granularity = 1, 95 95 .base_24_31 = 0 },
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