Changeset de7663f in mainline


Ignore:
Timestamp:
2007-06-13T18:39:31Z (17 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
341140c
Parents:
c03ee1c
Message:

Remove some forgotten \r from arm32 files.
Formatting changes.
Add some correct BOOT_mips32_* guards.

Files:
13 edited

Legend:

Unmodified
Added
Removed

  • boot/arch/arm32/loader/asm.h

    rc03ee1c rde7663f  
    6363 * @param bootinfo_size  Size of the bootinfo structure.
    6464 */
    65 extern void jump_to_kernel(void *entry, void *bootinfo, unsigned int bootinfo_size) __attribute__((noreturn));
     65extern void jump_to_kernel(void *entry, void *bootinfo,
     66    unsigned int bootinfo_size) __attribute__((noreturn));
    6667
    6768
    6869#endif
    6970
    70 
    7171/** @}
    7272 */
    73 

  • boot/arch/arm32/loader/main.h

    rc03ee1c rde7663f  
    6969
    7070
    71 
    7271extern void bootstrap(void);
    7372

  • boot/arch/arm32/loader/mm.c

    rc03ee1c rde7663f  
    4343 *  Will be readable/writable by kernel with no access from user mode.
    4444 *  Will belong to domain 0. No cache or buffering is enabled.
    45  *  
    46  *  @param pte    Section entry to initialize.
    47  *  @param frame  First frame in the section (frame number).
     45 *
     46 *  @param pte Section entry to initialize.
     47 *  @param frame First frame in the section (frame number).
    4848 *
    49  *  @note         If frame is not 1MB aligned, first lower 1MB aligned frame will be used.
    50  */   
    51 static void init_pte_level0_section(pte_level0_section_t* pte, unsigned int frame)
     49 *  @note If frame is not 1MB aligned, first lower 1MB aligned frame will be
     50 *      used.
     51 */
     52static void init_pte_level0_section(pte_level0_section_t* pte,
     53    unsigned int frame)
    5254{
    53         pte->descriptor_type   = PTE_DESCRIPTOR_SECTION;
    54         pte->bufferable        = 0;
    55         pte->cacheable         = 0;
    56         pte->impl_specific     = 0;
    57         pte->domain            = 0;
     55        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
     56        pte->bufferable = 0;
     57        pte->cacheable = 0;
     58        pte->impl_specific = 0;
     59        pte->domain = 0;
    5860        pte->should_be_zero_1  = 0;
    59         pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;     
     61        pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
    6062        pte->should_be_zero_2  = 0;
    6163        pte->section_base_addr = frame;
    6264}
    63 
    6465
    6566/** Initializes page table used while booting the kernel. */
    … …  
    6970        const unsigned int first_kernel_page = ADDR2PFN(PA2KA(0));
    7071
    71         // create 1:1 virtual-physical mapping (in lower 2GB)
     72        /* Create 1:1 virtual-physical mapping (in lower 2GB). */
    7273        for (i = 0; i < first_kernel_page; i++) {
    7374                init_pte_level0_section(&page_table[i], i);
    7475        }
    7576
    76         // create 1:1 virtual-physical mapping in kernel space (upper 2GB),
    77         // physical addresses start from 0
     77        /*
     78         * Create 1:1 virtual-physical mapping in kernel space (upper 2GB),
     79         * physical addresses start from 0.
     80         */
    7881        for (i = first_kernel_page; i < PTL0_ENTRIES; i++) {
    7982                init_pte_level0_section(&page_table[i], i - first_kernel_page);
    8083        }
    8184}
    82 
    8385
    8486/** Starts the MMU - initializes page table and enables paging. */
    … …  
    8991}
    9092
    91 
    9293/** @}
    9394 */
    94  
     95

  • boot/arch/arm32/loader/mm.h

    rc03ee1c rde7663f  
    11/*
    2  * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
     2 * Copyright (c) 2007 Pavel Jancik
     3 * Copyright (c) 2007 Michal Kebrt
    34 * All rights reserved.
    45 *
    … …  
    3435 *  @brief Memory management used while booting the kernel.
    3536 *
    36  *  So called "section" paging is used while booting the kernel. The term "section"
    37  *  comes from the ARM architecture specification and stands for the following:
    38  *  one-level paging, 1MB sized pages, 4096 entries in the page table.
     37 *  So called "section" paging is used while booting the kernel. The term
     38 *  "section" comes from the ARM architecture specification and stands for the
     39 *  following: one-level paging, 1MB sized pages, 4096 entries in the page
     40 *  table.
    3941 */
    4042
    … …  
    5052
    5153/** Frame width. */
    52 #define FRAME_WIDTH                 20
     54#define FRAME_WIDTH                     20
    5355
    5456/** Frame size. */
    55 #define FRAME_SIZE                  (1 << FRAME_WIDTH)
     57#define FRAME_SIZE                      (1 << FRAME_WIDTH)
    5658
    57 /** Page size in 2-level paging which is switched on later after the kernel initialization. */
    58 #define KERNEL_PAGE_SIZE            (1 << 12)
     59/** Page size in 2-level paging which is switched on later after the kernel
     60 * initialization.
     61 */
     62#define KERNEL_PAGE_SIZE                (1 << 12)
    5963
    6064
    6165#ifndef __ASM__
    6266/** Converts kernel address to physical address. */
    63 #       define KA2PA(x)                 (((uintptr_t) (x)) - 0x80000000)
     67#       define KA2PA(x)                 (((uintptr_t) (x)) - 0x80000000)
    6468/** Converts physical address to kernel address. */
    65 #       define PA2KA(x)                 (((uintptr_t) (x)) + 0x80000000)
     69#       define PA2KA(x)                 (((uintptr_t) (x)) + 0x80000000)
    6670#else
    67 #       define KA2PA(x)                 ((x) - 0x80000000)
    68 #       define PA2KA(x)                 ((x) + 0x80000000)
     71#       define KA2PA(x)                 ((x) - 0x80000000)
     72#       define PA2KA(x)                 ((x) + 0x80000000)
    6973#endif
    7074
    7175
    7276/** Number of entries in PTL0. */
    73 #define PTL0_ENTRIES                (1<<12)                             /* 4096 */
     77#define PTL0_ENTRIES                    (1 << 12)       /* 4096 */
    7478
    7579/** Size of an entry in PTL0. */
    76 #define PTL0_ENTRY_SIZE             4
     80#define PTL0_ENTRY_SIZE                 4
    7781
    7882/** Returns number of frame the address belongs to. */
    79 #define ADDR2PFN( addr )            ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
     83#define ADDR2PFN(addr)                  (((uintptr_t) (addr)) >> FRAME_WIDTH)
    8084
    8185/** Describes "section" page table entry (one-level paging with 1MB sized pages). */ 
    82 #define PTE_DESCRIPTOR_SECTION      0x2
     86#define PTE_DESCRIPTOR_SECTION          0x2
    8387
    8488/** Page table access rights: user - no access, kernel - read/write. */
    85 #define PTE_AP_USER_NO_KERNEL_RW    0x1
     89#define PTE_AP_USER_NO_KERNEL_RW        0x1
    8690
    8791
    … …  
    8993
    9094
    91 /** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
    92  * pages). Used only while booting the kernel.
     95/** Page table level 0 entry - "section" format is used (one-level paging, 1MB
     96 * sized pages). Used only while booting the kernel.
    9397 */
    9498typedef struct {
    95         unsigned descriptor_type     : 2;
    96         unsigned bufferable          : 1;
    97         unsigned cacheable           : 1;
    98         unsigned impl_specific       : 1;
    99         unsigned domain              : 4;
    100         unsigned should_be_zero_1    : 1;
    101         unsigned access_permission   : 2;       
    102         unsigned should_be_zero_2    : 8;
    103         unsigned section_base_addr   : 12;
     99        unsigned descriptor_type : 2;
     100        unsigned bufferable : 1;
     101        unsigned cacheable : 1;
     102        unsigned impl_specific : 1;
     103        unsigned domain : 4;
     104        unsigned should_be_zero_1 : 1;
     105        unsigned access_permission : 2;         
     106        unsigned should_be_zero_2 : 8;
     107        unsigned section_base_addr : 12;
    104108} __attribute__ ((packed)) pte_level0_section_t;
    105109
    106110
    107 /** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
     111/** Page table that holds 1:1 virtual to physical mapping used while booting the
     112 * kernel.
     113 */
    108114extern pte_level0_section_t page_table[PTL0_ENTRIES];
    109115
    … …  
    118124         */
    119125        asm volatile (
    120                 // behave as a client of domains
    121                 "ldr r0, =0x55555555       \n"
    122                 "mcr p15, 0, r0, c3, c0, 0 \n"
     126                /* behave as a client of domains */
     127                "ldr r0, =0x55555555\n"
     128                "mcr p15, 0, r0, c3, c0, 0\n"
    123129
    124                 // current settings
    125                 "mrc p15, 0, r0, c1, c0, 0 \n"
     130                /* current settings */
     131                "mrc p15, 0, r0, c1, c0, 0\n"
    126132
    127                 // mask to enable paging
    128                 "ldr r1, =0x00000001       \n"
    129                 "orr r0, r0, r1            \n"
     133                /* mask to enable paging */
     134                "ldr r1, =0x00000001\n"
     135                "orr r0, r0, r1\n"
    130136
    131                 // store settings
    132                 "mcr p15, 0, r0, c1, c0, 0 \n"
     137                /* store settings */
     138                "mcr p15, 0, r0, c1, c0, 0\n"
    133139                :
    134140                :
    … …  
    144150static inline void set_ptl0_address(pte_level0_section_t* pt)
    145151{
    146     asm volatile (
    147                 "mcr p15, 0, %0, c2, c0, 0 \n"
     152        asm volatile (
     153                "mcr p15, 0, %0, c2, c0, 0\n"
    148154                :
    149                 : "r"(pt)
    150     );
     155                : "r" (pt)
     156        );
    151157}
    152158

  • boot/arch/arm32/loader/print/gxemul.c

    rc03ee1c rde7663f  
    4949static void putc(char ch)
    5050{
    51         *((volatile char *)PUTC_ADDRESS) = ch;
     51        *((volatile char *) PUTC_ADDRESS) = ch;
    5252}
    5353

  • boot/arch/arm32/loader/types.h

    rc03ee1c rde7663f  
    5858/** @}
    5959 */
    60 

  • boot/arch/mips32/loader/asm.h

    rc03ee1c rde7663f  
    2727 */
    2828
    29 #ifndef __ASM_H__
    30 #define __ASM_H__
     29#ifndef BOOT_mips32_ASM_H_
     30#define BOOT_mips32_ASM_H_
    3131
    3232#define PAGE_SIZE 16384
    3333#define PAGE_WIDTH 14
    3434
    35 #define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
     35#define memcpy(dst, src, cnt)   __builtin_memcpy((dst), (src), (cnt))
    3636
    3737void jump_to_kernel(void *entry, void *bootinfo, unsigned int bootinfo_size) __attribute__((noreturn));

  • boot/arch/mips32/loader/main.h

    rc03ee1c rde7663f  
    2727 */
    2828
    29 #ifndef __MAIN_H__
    30 #define __MAIN_H__
     29#ifndef BOOT_mips32_MAIN_H_
     30#define BOOT_mips32_MAIN_H_
    3131
    3232/** Align to the nearest higher address.

  • boot/arch/mips32/loader/msim.h

    rc03ee1c rde7663f  
    2727 */
    2828
    29 #ifndef __MSIM_H__
    30 #define __MSIM_H__
     29#ifndef BOOT_mips32_MSIM_H_
     30#define BOOT_mips32_MSIM_H_
    3131
    3232extern void init(void);

  • boot/arch/mips32/loader/regname.h

    rc03ee1c rde7663f  
    2727 */
    2828
    29 #ifndef __mips32_REGNAME_H_
    30 #define __mips32_REGNAME_H_
     29#ifndef BOOT_mips32_REGNAME_H_
     30#define BOOT_mips32_REGNAME_H_
    3131
    3232#define zero    0
    … …  
    8686#define eepc            30
    8787
    88 
    8988#endif /* _REGNAME_H_ */

  • boot/arch/mips32/loader/types.h

    rc03ee1c rde7663f  
    2727 */
    2828
    29 #ifndef TYPES_H__
    30 #define TYPES_H__
     29#ifndef BOOT_mips32_TYPES_H_
     30#define BOOT_mips32_TYPES_H_
    3131
    3232#include <gentypes.h>

  • uspace/libc/arch/arm32/include/atomic.h

    rc03ee1c rde7663f  
    5050
    5151        asm volatile (
    52                 "1:                 \n"
    53                 "ldr r2, [%1]       \n"
    54                 "add r3, r2, %2     \n"
    55                 "str r3, %0         \n"
    56                 "swp r3, r3, [%1]   \n"
    57                 "cmp r3, r2         \n"
    58                 "bne 1b             \n"
     52        "1:\n"
     53                "ldr r2, [%1]\n"
     54                "add r3, r2, %2\n"
     55                "str r3, %0\n"
     56                "swp r3, r3, [%1]\n"
     57                "cmp r3, r2\n"
     58                "bne 1b\n"
    5959
    6060                : "=m" (ret)
    … …  
    7171 * @param val Variable to be incremented.
    7272 */
    73 static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); }
     73static inline void atomic_inc(atomic_t *val)
     74{
     75        atomic_add(val, 1);
     76}
    7477
    7578
    … …  
    7881 * @param val Variable to be decremented.
    7982 */
    80 static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
     83static inline void atomic_dec(atomic_t *val)
     84{
     85        atomic_add(val, -1);
     86}
    8187
    8288
    … …  
    8692 * @return    Value after incrementation.
    8793 */
    88 static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); }
     94static inline long atomic_preinc(atomic_t *val)
     95{
     96        return atomic_add(val, 1);
     97}
    8998
    9099
    … …  
    94103 * @return    Value after decrementation.
    95104 */
    96 static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); }
     105static inline long atomic_predec(atomic_t *val)
     106{
     107        return atomic_add(val, -1);
     108}
    97109
    98110
    … …  
    102114 * @return    Value before incrementation.
    103115 */
    104 static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; }
     116static inline long atomic_postinc(atomic_t *val)
     117{
     118        return atomic_add(val, 1) - 1;
     119}
    105120
    106121
    … …  
    110125 * @return    Value before decrementation.
    111126 */
    112 static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; }
     127static inline long atomic_postdec(atomic_t *val)
     128{
     129        return atomic_add(val, -1) + 1;
     130}
    113131
    114132

  • uspace/libc/arch/arm32/include/thread.h

    rc03ee1c rde7663f  
    6161static inline void __tcb_set(tcb_t *tcb)
    6262{
    63         void *tls = (void *)tcb;
     63        void *tls = (void *) tcb;
    6464        tls += sizeof(tcb_t) + ARM_TP_OFFSET;
    6565        asm volatile (
    … …  
    8282                : "=r"(ret)
    8383        );
    84         return (tcb_t *)(ret - ARM_TP_OFFSET - sizeof(tcb_t));
     84        return (tcb_t *) (ret - ARM_TP_OFFSET - sizeof(tcb_t));
    8585}
    8686
Note: See TracChangeset for help on using the changeset viewer.