Changes in boot/arch/arm32/src/mm.c [5e761f3:df334ca] in mainline

File:

• boot/arch/arm32/src/mm.c (modified) (5 diffs)

boot/arch/arm32/src/mm.c

@@ -38 +38 @@
 #include <arch/mm.h>
 
-/** Disable the MMU */
-static void disable_paging(void)
-{
-        asm volatile (
-                "mrc p15, 0, r0, c1, c0, 0\n"
-                "bic r0, r0, #1\n"
-                "mcr p15, 0, r0, c1, c0, 0\n"
-        );
-}
-
 /** Check if caching can be enabled for a given memory section.
  *
@@ -66 +56 @@
         else
                 return 1;
-#else
+#elif defined MACHINE_beagleboardxm
+        const unsigned long address = section << PTE_SECTION_SHIFT;
+        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
+                return 1;
+#endif
         return 0;
-#endif
 }
 
@@ -110 +103 @@
                 init_ptl0_section(&boot_pt[page], page);
         
+        /*
+         * Create 1:1 virtual-physical mapping in kernel space
+         * (upper 2 GB), physical addresses start from 0.
+         */
+        /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
+         * thus mapping only lower 2GB is not not enough.
+         * Map entire AS 1:1 instead and hope it works. */
+        for (page = split_page; page < PTL0_ENTRIES; page++)
+#ifndef MACHINE_beagleboardxm
+                init_ptl0_section(&boot_pt[page], page - split_page);
+#else
+                init_ptl0_section(&boot_pt[page], page);
+#endif
+        
         asm volatile (
                 "mcr p15, 0, %[pt], c2, c0, 0\n"
@@ -125 +132 @@
                 "ldr r0, =0x55555555\n"
                 "mcr p15, 0, r0, c3, c0, 0\n"
-
+                
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#ifdef PROCESSOR_armv7_a
-                /* Mask to enable paging, caching */
-                "ldr r1, =0x00000005\n"
-#else
-#ifdef MACHINE_gta02
-                /* Mask to enable paging (bit 0),
-                   D-cache (bit 2), I-cache (bit 12) */
-                "ldr r1, =0x00001005\n"
-#else
-                /* Mask to enable paging */
-                "ldr r1, =0x00000001\n"
-#endif
-#endif
+                /* Enable ICache, DCache, BPredictors and MMU,
+                 * we disable caches before jumping to kernel
+                 * so this is safe for all archs.
+                 */
+                "ldr r1, =0x00001805\n"
+                
                 "orr r0, r0, r1\n"
-
-                /* Flush the TLB */
-                "mcr p15, 0, r0, c8, c7, 0\n"
                 
-                /* Store settings, enable the MMU */
+                /* Store settings */
                 "mcr p15, 0, r0, c1, c0, 0\n"
                 ::: "r0", "r1"
@@ -155 +152 @@
 /** Start the MMU - initialize page table and enable paging. */
 void mmu_start() {
-        disable_paging();
         init_boot_pt();
         enable_paging();