Changes in boot/arch/arm32/src/mm.c [9d58539:df334ca] in mainline

File:

• boot/arch/arm32/src/mm.c (modified) (5 diffs)

boot/arch/arm32/src/mm.c

@@ -38 +38 @@
 #include <arch/mm.h>
 
+/** Check if caching can be enabled for a given memory section.
+ *
+ * Memory areas used for I/O are excluded from caching.
+ * At the moment caching is enabled only on GTA02.
+ *
+ * @param section       The section number.
+ *
+ * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
+*/
+static inline int section_cacheable(pfn_t section)
+{
+#ifdef MACHINE_gta02
+        unsigned long address = section << PTE_SECTION_SHIFT;
+
+        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
+                return 0;
+        else
+                return 1;
+#elif defined MACHINE_beagleboardxm
+        const unsigned long address = section << PTE_SECTION_SHIFT;
+        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
+                return 1;
+#endif
+        return 0;
+}
+
 /** Initialize "section" page table entry.
  *
@@ -54 +80 @@
 {
         pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
-        pte->bufferable = 0;
-        pte->cacheable = 0;
-        pte->impl_specific = 0;
+        pte->bufferable = 1;
+        pte->cacheable = section_cacheable(frame);
+        pte->xn = 0;
         pte->domain = 0;
         pte->should_be_zero_1 = 0;
-        pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
+        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
+        pte->tex = 0;
+        pte->access_permission_1 = 0;
+        pte->non_global = 0;
         pte->should_be_zero_2 = 0;
+        pte->non_secure = 0;
         pte->section_base_addr = frame;
 }
@@ -67 +97 @@
 static void init_boot_pt(void)
 {
-        pfn_t split_page = 0x800;
-        
+        const pfn_t split_page = PTL0_ENTRIES;
         /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
         pfn_t page;
@@ -78 +107 @@
          * (upper 2 GB), physical addresses start from 0.
          */
+        /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
+         * thus mapping only lower 2GB is not not enough.
+         * Map entire AS 1:1 instead and hope it works. */
         for (page = split_page; page < PTL0_ENTRIES; page++)
+#ifndef MACHINE_beagleboardxm
                 init_ptl0_section(&boot_pt[page], page - split_page);
+#else
+                init_ptl0_section(&boot_pt[page], page);
+#endif
         
         asm volatile (
@@ -95 +131 @@
                 /* Behave as a client of domains */
                 "ldr r0, =0x55555555\n"
-                "mcr p15, 0, r0, c3, c0, 0\n" 
+                "mcr p15, 0, r0, c3, c0, 0\n"
                 
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-                /* Mask to enable paging */
-                "ldr r1, =0x00000001\n"
+                /* Enable ICache, DCache, BPredictors and MMU,
+                 * we disable caches before jumping to kernel
+                 * so this is safe for all archs.
+                 */
+                "ldr r1, =0x00001805\n"
+                
                 "orr r0, r0, r1\n"