Changes in boot/arch/arm32/src/mm.c [b5a3b50:df334ca] in mainline

File:

• boot/arch/arm32/src/mm.c (modified) (2 diffs)

boot/arch/arm32/src/mm.c

@@ -56 +56 @@
         else
                 return 1;
-#else
+#elif defined MACHINE_beagleboardxm
+        const unsigned long address = section << PTE_SECTION_SHIFT;
+        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
+                return 1;
+#endif
         return 0;
-#endif
 }
 
@@ -130 +133 @@
                 "mcr p15, 0, r0, c3, c0, 0\n"
                 
-#ifdef PROCESSOR_armv7_a
-                /* Read Auxiliary control register */
-                "mrc p15, 0, r0, c1, c0, 1\n"
-                /* Mask to enable L2 cache */
-                "ldr r1, =0x00000002\n"
-                "orr r0, r0, r1\n"
-                /* Store Auxiliary control register */
-                "mrc p15, 0, r0, c1, c0, 1\n"
-#endif
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#ifdef PROCESSOR_armv7_a
-                /* Mask to enable paging, caching */
-                "ldr r1, =0x00000005\n"
-#else
-#ifdef MACHINE_gta02
-                /* Mask to enable paging (bit 0),
-                   D-cache (bit 2), I-cache (bit 12) */
-                "ldr r1, =0x00001005\n"
-#else
-                /* Mask to enable paging */
-                "ldr r1, =0x00000001\n"
-#endif
-#endif
+                /* Enable ICache, DCache, BPredictors and MMU,
+                 * we disable caches before jumping to kernel
+                 * so this is safe for all archs.
+                 */
+                "ldr r1, =0x00001805\n"
+                
                 "orr r0, r0, r1\n"