Changes in / [6db5d4b:dff90fa7] in mainline

Files:

• boot/arch/arm32/src/asm.S (modified) (1 diff)
• boot/arch/arm32/src/main.c (modified) (5 diffs)
• kernel/genarch/include/genarch/drivers/amdm37x_uart/amdm37x_uart.h (added)
• kernel/genarch/include/genarch/fb/logo-196x66.h (added)

boot/arch/arm32/src/asm.S

@@ -71 +71 @@
         mrc     p15, 0, r4, c1, c0, 0
         bic     r4, r4, #(1 << CP15_C1_DC)
+#ifndef PROCESSOR_ARCH_armv7_a
         bic     r4, r4, #(1 << CP15_C1_IC)
         bic     r4, r4, #(1 << CP15_C1_BP)
+#endif
         mcr     p15, 0, r4, c1, c0, 0
 

boot/arch/arm32/src/main.c

@@ -63 +63 @@
 {
         const uintptr_t addr = (uintptr_t)address;
-        /* DCIMVAC - invalidate by address to the point of coherence */
         for (uintptr_t a = addr; a < addr + size; a += 4) {
+                /* DCIMVAC - invalidate by address to the point of coherence */
                 asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
         }
@@ -72 +72 @@
 {
         const uintptr_t addr = (uintptr_t)address;
-        /* DCCMVAC - clean by address to the point of coherence */
         for (uintptr_t a = addr; a < addr + size; a += 4) {
+                /* DCCMVAC - clean by address to the point of coherence */
                 asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
         }
@@ -82 +82 @@
 void bootstrap(void)
 {
-        /* Make sure  we run in memory code when caches are enabled,
+        /* Make sure we run in memory code when caches are enabled,
          * make sure we read memory data too. This part is ARMv7 specific as
          * ARMv7 no longer invalidates caches on restart.
@@ -105 +105 @@
                     components[i].start, components[i].name, components[i].inflated,
                     components[i].size);
+                /* Make sure there is no cache garbage in read locations */
                 invalidate_dcache(components[i].start, components[i].size);
         }
@@ -148 +149 @@
                         halt();
                 }
+                /* Make sure data are in the memory, ICache will need them */
                 clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
         }