Changeset e12ccc5 in mainline for kernel/arch/xen32/src/mm/frame.c
- Timestamp:
- 2006-08-01T17:27:11Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0fbfa0d
- Parents:
- e386cbf
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/xen32/src/mm/frame.c
re386cbf re12ccc5 35 35 36 36 #include <mm/frame.h> 37 #include <arch/mm/frame.h>38 #include <mm/as.h>39 37 #include <config.h> 40 #include <arch/boot/boot.h>41 #include <arch/hypercall.h>42 #include <panic.h>43 #include <debug.h>44 #include <align.h>45 #include <macros.h>46 47 #include <console/cmd.h>48 #include <console/kconsole.h>49 50 uintptr_t last_frame = 0;51 52 #define L0_PT_SHIFT 1053 #define L3_PT_SHIFT 054 55 #define L0_PT_ENTRIES 102456 #define L3_PT_ENTRIES 102457 58 #define L0_INDEX_MASK (L0_PT_ENTRIES - 1)59 #define L3_INDEX_MASK (L3_PT_ENTRIES - 1)60 61 #define PFN2PTL0_INDEX(pfn) ((pfn >> L0_PT_SHIFT) & L0_INDEX_MASK)62 #define PFN2PTL3_INDEX(pfn) ((pfn >> L3_PT_SHIFT) & L3_INDEX_MASK)63 64 #define PAGE_MASK (~(PAGE_SIZE - 1))65 66 #define _PAGE_PRESENT 0x001UL67 #define _PAGE_RW 0x002UL68 #define _PAGE_USER 0x004UL69 #define _PAGE_PWT 0x008UL70 #define _PAGE_PCD 0x010UL71 #define _PAGE_ACCESSED 0x020UL72 #define _PAGE_DIRTY 0x040UL73 #define _PAGE_PAT 0x080UL74 #define _PAGE_PSE 0x080UL75 #define _PAGE_GLOBAL 0x100UL76 77 #define L0_PROT (_PAGE_PRESENT | _PAGE_ACCESSED)78 #define L3_PROT (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED)79 38 80 39 void frame_arch_init(void) 81 40 { 82 41 if (config.cpu_active == 1) { 83 /* The only memory zone starts just after page table */ 84 pfn_t start = ADDR2PFN(ALIGN_UP(KA2PA(start_info.ptl0), PAGE_SIZE)) + start_info.pt_frames; 85 size_t size = start_info.frames - start; 86 87 /* Create identity mapping */ 88 pfn_t phys; 89 count_t count = 0; 90 for (phys = start; phys < start + size; phys++) { 91 mmu_update_t updates[L3_PT_ENTRIES]; 92 pfn_t virt = ADDR2PFN(PA2KA(PFN2ADDR(phys))); 93 94 size_t ptl0_index = PFN2PTL0_INDEX(virt); 95 size_t ptl3_index = PFN2PTL3_INDEX(virt); 96 97 pte_t *ptl3 = (pte_t *) PFN2ADDR(start_info.ptl0[ptl0_index].frame_address); 98 99 if (ptl3 == 0) { 100 mmuext_op_t mmu_ext; 101 102 pfn_t virt2 = ADDR2PFN(PA2KA(PFN2ADDR(start))); 103 104 /* New L1 page table entry needed */ 105 memsetb(PFN2ADDR(virt2), PAGE_SIZE, 0); 106 107 size_t ptl0_index2 = PFN2PTL0_INDEX(virt2); 108 size_t ptl3_index2 = PFN2PTL3_INDEX(virt2); 109 pte_t *ptl3_2 = (pte_t *) PFN2ADDR(start_info.ptl0[ptl0_index2].frame_address); 110 111 if (ptl3_2 == 0) 112 panic("Unable to find page table reference"); 113 114 updates[count].ptr = (uintptr_t) &ptl3_2[ptl3_index2]; 115 updates[count].val = PA2MA(PFN2ADDR(start)) | L0_PROT; 116 if (xen_mmu_update(updates, count + 1, NULL, DOMID_SELF) < 0) 117 panic("Unable to map new page table"); 118 count = 0; 119 120 mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; 121 mmu_ext.arg1.mfn = ADDR2PFN(PA2MA(PFN2ADDR(start))); 122 if (xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) < 0) 123 panic("Error pinning new page table"); 124 125 pte_t *ptl0 = (pte_t *) PA2MA(KA2PA(start_info.ptl0)); 126 127 updates[count].ptr = (uintptr_t) &ptl0[ptl0_index]; 128 updates[count].val = PA2MA(PFN2ADDR(start)) | L3_PROT; 129 if (xen_mmu_update(updates, count + 1, NULL, DOMID_SELF) < 0) 130 panic("Unable to update PTE for page table"); 131 count = 0; 132 133 ptl3 = (pte_t *) PFN2ADDR(start_info.ptl0[ptl0_index].frame_address); 134 start++; 135 size--; 136 } 137 138 updates[count].ptr = (uintptr_t) &ptl3[ptl3_index]; 139 updates[count].val = PA2MA(PFN2ADDR(phys)) | L3_PROT; 140 count++; 141 142 if ((count == L3_PT_ENTRIES) || (phys + 1 == start + size)) { 143 if (xen_mmu_update(updates, count, NULL, DOMID_SELF) < 0) 144 panic("Unable to update PTE"); 145 count = 0; 146 } 147 } 148 149 zone_create(start, size, start, 0); 150 last_frame = start + size; 42 /* The only memory zone */ 43 zone_create(meminfo.start, meminfo.size, meminfo.start + meminfo.reserved, 0); 44 frame_mark_unavailable(meminfo.start, meminfo.reserved); 151 45 } 152 46 }
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