Changeset e1be3b6 in mainline


Ignore:
Timestamp:
2006-03-23T21:18:58Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9cbd27b
Parents:
3b712407
Message:

Small textual changes.

Files:
8 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/include/atomic.h

    r3b712407 re1be3b6  
    102102                "0:;"
    103103#ifdef CONFIG_HT
    104                 "pause;" /* Pentium 4's HT love this instruction */
     104                "pause;"
    105105#endif
    106106                "mov %0, %1;"

  • arch/amd64/src/amd64.c

    r3b712407 re1be3b6  
    164164}
    165165
    166 /** Set Thread-local-storeage pointer
     166/** Set thread-local-storage pointer
    167167 *
    168168 * TLS pointer is set in FS register. Unfortunately the 64-bit
    169169 * part can be set only in CPL0 mode.
    170170 *
    171  * The specs says, that on %fs:0 there is stored contents of %fs register,
     171 * The specs say, that on %fs:0 there is stored contents of %fs register,
    172172 * we need not to go to CPL0 to read it.
    173173 */

  • arch/amd64/src/asm_utils.S

    r3b712407 re1be3b6  
    181181         * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
    182182         * can result in two instructions with different op-code lengths.
    183          * Therefore, pay special attention to the extra NOP's that serve as
    184          * a necessary fill.
     183         * Therefore we align the interrupt handlers.
    185184         */
    186185

  • arch/ia32/src/ia32.c

    r3b712407 re1be3b6  
    110110}
    111111
    112 /** Set Thread-local-storeage pointer
     112/** Set thread-local-storage pointer
    113113 *
    114114 * TLS pointer is set in GS register. That means, the GS contains

  • arch/ia32/src/userspace.c

    r3b712407 re1be3b6  
    4343{
    4444        ipl_t ipl;
    45        
     45
    4646        ipl = interrupts_disable();
    4747

  • arch/ia64/src/ia64.c

    r3b712407 re1be3b6  
    4343#include <console/console.h>
    4444#include <proc/uarg.h>
     45#include <syscall/syscall.h>
    4546
    4647void arch_pre_mm_init(void)
    … …  
    102103        }
    103104}
     105
     106/** Set thread-local-storage pointer.
     107 *
     108 * We use r13 (a.k.a. tp) for this purpose.
     109 */
     110__native sys_tls_set(__native addr)
     111{
     112        return 0;
     113}

  • arch/mips32/src/mips32.c

    r3b712407 re1be3b6  
    144144}
    145145
    146 /** Set Thread-local-storeage pointer
     146/** Set thread-local-storage pointer
    147147 *
    148148 * We have it currently in K1, it is

  • generic/src/adt/btree.c

    r3b712407 re1be3b6  
    2929/*
    3030 * This B-tree has the following properties:
    31  * - it is a ballanced 2-3-4 tree (i.e. M = 4)
     31 * - it is a ballanced 2-3-4 tree (i.e. BTREE_M = 4)
    3232 * - values (i.e. pointers to values) are stored only in leaves
    3333 * - leaves are linked in a list
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