Changes in kernel/arch/ia32/src/smp/smp.c [99718a2e:e3ce39b] in mainline
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kernel/arch/ia32/src/smp/smp.c
r99718a2e re3ce39b 62 62 void smp_init(void) 63 63 { 64 uintptr_t l_apic_address, io_apic_address; 65 64 66 if (acpi_madt) { 65 67 acpi_madt_parse(); 66 68 ops = &madt_config_operations; 67 69 } 68 69 70 if (config.cpu_count == 1) { 70 71 mps_init(); 71 72 ops = &mps_config_operations; 72 73 } 73 74 75 l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, 76 FRAME_ATOMIC | FRAME_KA); 77 if (!l_apic_address) 78 panic("Cannot allocate address for l_apic."); 79 80 io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, 81 FRAME_ATOMIC | FRAME_KA); 82 if (!io_apic_address) 83 panic("Cannot allocate address for io_apic."); 84 74 85 if (config.cpu_count > 1) { 75 l_apic = (uint32_t *) hw_map((uintptr_t) l_apic, PAGE_SIZE); 76 io_apic = (uint32_t *) hw_map((uintptr_t) io_apic, PAGE_SIZE); 86 page_table_lock(AS_KERNEL, true); 87 page_mapping_insert(AS_KERNEL, l_apic_address, 88 (uintptr_t) l_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); 89 page_mapping_insert(AS_KERNEL, io_apic_address, 90 (uintptr_t) io_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); 91 page_table_unlock(AS_KERNEL, true); 92 93 l_apic = (uint32_t *) l_apic_address; 94 io_apic = (uint32_t *) io_apic_address; 77 95 } 78 96 } … … 90 108 91 109 ASSERT(ops != NULL); 92 110 93 111 /* 94 112 * We need to access data in frame 0. 95 113 * We boldly make use of kernel address space mapping. 96 114 */ 97 115 98 116 /* 99 117 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot() 100 118 */ 101 119 *((uint16_t *) (PA2KA(0x467 + 0))) = 102 (uint16_t) (((uintptr_t) ap_boot) >> 4); 103 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; 120 (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */ 121 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */ 104 122 105 123 /* … … 107 125 * BIOS will not do the POST after the INIT signal. 108 126 */ 109 pio_write_8((ioport8_t *) 110 pio_write_8((ioport8_t *) 111 127 pio_write_8((ioport8_t *)0x70, 0xf); 128 pio_write_8((ioport8_t *)0x71, 0xa); 129 112 130 pic_disable_irqs(0xffff); 113 131 apic_init(); 114 132 115 for (i = 0; i < config.cpu_count; i++) { 133 uint8_t apic = l_apic_id(); 134 135 for (i = 0; i < ops->cpu_count(); i++) { 136 descriptor_t *gdt_new; 137 116 138 /* 117 139 * Skip processors marked unusable. … … 119 141 if (!ops->cpu_enabled(i)) 120 142 continue; 121 143 122 144 /* 123 145 * The bootstrap processor is already up. … … 125 147 if (ops->cpu_bootstrap(i)) 126 148 continue; 127 128 if (ops->cpu_apic_id(i) == bsp_l_apic) {129 printf(" kmp: bad processor entry #%u, will not send IPI "130 "to myself\n", i);149 150 if (ops->cpu_apic_id(i) == apic) { 151 printf("%s: bad processor entry #%u, will not send IPI " 152 "to myself\n", __FUNCTION__, i); 131 153 continue; 132 154 } … … 140 162 * the memory subsystem 141 163 */ 142 descriptor_t *gdt_new = 143 (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t), 144 FRAME_ATOMIC); 164 gdt_new = (descriptor_t *) malloc(GDT_ITEMS * 165 sizeof(descriptor_t), FRAME_ATOMIC); 145 166 if (!gdt_new) 146 167 panic("Cannot allocate memory for GDT."); 147 168 148 169 memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t)); 149 170 memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0); … … 151 172 protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new); 152 173 gdtr.base = (uintptr_t) gdt_new; 153 174 154 175 if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) { 155 176 /* … … 160 181 if (waitq_sleep_timeout(&ap_completion_wq, 1000000, 161 182 SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) { 183 unsigned int cpu = (config.cpu_active > i) ? 184 config.cpu_active : i; 162 185 printf("%s: waiting for cpu%u (APIC ID = %d) " 163 "timed out\n", __FUNCTION__, i,186 "timed out\n", __FUNCTION__, cpu, 164 187 ops->cpu_apic_id(i)); 165 188 }
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