Changeset e41455d in mainline

Timestamp:

2007-04-17T18:53:58Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2e915f2

Parents:

9a7a970

Message:

Add few assertions to tsb.c and clean it up a little bit.

File:

• kernel/arch/sparc64/src/mm/tsb.c (modified) (5 diffs)

kernel/arch/sparc64/src/mm/tsb.c

@@ -62 +62 @@
         
         i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
+        ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
+
         if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
                 cnt = ITSB_ENTRY_COUNT;
@@ -85 +87 @@
         tsb_entry_t *tsb;
         index_t entry;
+
+        ASSERT(index <= 1);
         
         as = t->as;
         entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; 
+        ASSERT(entry < ITSB_ENTRY_COUNT);
         tsb = &as->arch.itsb[entry];
 
@@ -103 +108 @@
 
         tsb->tag.context = as->asid;
-        tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
-            VA_TAG_PAGE_SHIFT;
+        /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
+        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
         tsb->data.value = 0;
         tsb->data.size = PAGESIZE_8K;
@@ -129 +134 @@
         index_t entry;
         
+        ASSERT(index <= 1);
+
         as = t->as;
         entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
+        ASSERT(entry < DTSB_ENTRY_COUNT);
         tsb = &as->arch.dtsb[entry];
 
@@ -146 +154 @@
 
         tsb->tag.context = as->asid;
-        tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
-            VA_TAG_PAGE_SHIFT;
+        /* the shift is bigger than PAGE_WIDTH, do not bother with index */
+        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
         tsb->data.value = 0;
         tsb->data.size = PAGESIZE_8K;