Changes in kernel/arch/ia64/src/asm.S [da52547:e4a4b44] in mainline
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kernel/arch/ia64/src/asm.S
rda52547 re4a4b44 1 /* 2 *Copyright (c) 2005 Jakub Jermar3 *All rights reserved.4 * 5 *Redistribution and use in source and binary forms, with or without6 *modification, are permitted provided that the following conditions7 *are met:8 * 9 *- Redistributions of source code must retain the above copyright10 *notice, this list of conditions and the following disclaimer.11 *- Redistributions in binary form must reproduce the above copyright12 *notice, this list of conditions and the following disclaimer in the13 *documentation and/or other materials provided with the distribution.14 *- The name of the author may not be used to endorse or promote products15 *derived from this software without specific prior written permission.16 * 17 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR18 *IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES19 *OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.20 *IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,21 *INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT22 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,23 *DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY24 *THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT25 *(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF26 *THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.27 */ 1 # 2 # Copyright (c) 2005 Jakub Jermar 3 # All rights reserved. 4 # 5 # Redistribution and use in source and binary forms, with or without 6 # modification, are permitted provided that the following conditions 7 # are met: 8 # 9 # - Redistributions of source code must retain the above copyright 10 # notice, this list of conditions and the following disclaimer. 11 # - Redistributions in binary form must reproduce the above copyright 12 # notice, this list of conditions and the following disclaimer in the 13 # documentation and/or other materials provided with the distribution. 14 # - The name of the author may not be used to endorse or promote products 15 # derived from this software without specific prior written permission. 16 # 17 # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 # 28 28 29 29 #include <arch/register.h> 30 30 31 31 .text 32 .global memcpy33 .global memcpy_from_uspace34 .global memcpy_to_uspace35 .global memcpy_from_uspace_failover_address36 .global memcpy_to_uspace_failover_address37 32 38 33 /** Copy memory from/to userspace. … … 44 39 * @param in1 Source address. 45 40 * @param in2 Number of byte to copy. 46 *47 41 */ 42 .global memcpy 43 .global memcpy_from_uspace 44 .global memcpy_to_uspace 45 .global memcpy_from_uspace_failover_address 46 .global memcpy_to_uspace_failover_address 48 47 memcpy: 49 48 memcpy_from_uspace: 50 49 memcpy_to_uspace: 51 50 alloc loc0 = ar.pfs, 3, 1, 0, 0 52 51 53 52 adds r14 = 7, in1 54 53 mov r2 = ar.lc … … 56 55 and r14 = -8, r14 ;; 57 56 cmp.ne p6, p7 = r14, in1 58 (p7) br.cond.dpnt 3f ;; 57 (p7) br.cond.dpnt 3f ;; 58 0: 59 cmp.ne p6, p7 = 0, in2 60 (p7) br.cond.dpnt 2f ;; 61 (p6) adds r14 = -1, in2 62 (p6) mov r16 = r0 63 (p6) mov r17 = r0 ;; 64 (p6) mov ar.lc = r14 65 1: 66 add r14 = r16, in1 67 add r15 = r16, in0 68 adds r17 = 1, r17 ;; 69 ld1 r14 = [r14] 70 mov r16 = r17 ;; 71 st1 [r15] = r14 72 br.cloop.sptk.few 1b ;; 73 2: 74 mov ar.lc = r2 75 mov ar.pfs = loc0 76 br.ret.sptk.many rp 77 3: 78 adds r14 = 7, in0 ;; 79 and r14 = -8, r14 ;; 80 cmp.eq p6, p7 = r14, in0 81 (p7) br.cond.dptk 0b 82 shr.u r18 = in2, 3 ;; 83 cmp.ne p6, p7 = 0, r18 84 (p7) br.cond.dpnt 5f ;; 85 (p6) adds r14 = -1, r18 86 (p6) mov r16 = r0 87 (p6) mov r17 = r0 ;; 88 (p6) mov ar.lc = r14 89 4: 90 shladd r14 = r16, 3, r0 91 adds r16 = 1, r17 ;; 92 add r15 = in1, r14 93 add r14 = in0, r14 94 mov r17 = r16 ;; 95 ld8 r15 = [r15] ;; 96 st8 [r14] = r15 97 br.cloop.sptk.few 4b 98 5: 99 and r15 = 7, in2 100 shladd r14 = r18, 3, r0 101 mov r16 = r0 102 mov r18 = r0 ;; 103 cmp.eq p6, p7 = 0, r15 104 add in0 = r14, in0 105 adds r15 = -1, r15 106 add r17 = r14, in1 107 (p6) br.cond.dpnt 2b ;; 108 mov ar.lc = r15 109 6: 110 add r14 = r16, r17 111 add r15 = r16, in0 112 adds r16 = 1, r18 ;; 113 ld1 r14 = [r14] 114 mov r18 = r16 ;; 115 st1 [r15] = r14 116 br.cloop.sptk.few 6b ;; 117 mov ar.lc = r2 118 mov ar.pfs = loc0 119 br.ret.sptk.many rp 59 120 60 0:61 62 cmp.ne p6, p7 = 0, in263 (p7) br.cond.dpnt 2f ;;64 (p6) adds r14 = -1, in265 (p6) mov r16 = r066 (p6) mov r17 = r0 ;;67 (p6) mov ar.lc = r1468 69 1:70 71 add r14 = r16, in172 add r15 = r16, in073 adds r17 = 1, r17 ;;74 ld1 r14 = [r14]75 mov r16 = r17 ;;76 st1 [r15] = r1477 br.cloop.sptk.few 1b ;;78 79 2:80 81 mov ar.lc = r282 mov ar.pfs = loc083 br.ret.sptk.many rp84 85 3:86 87 adds r14 = 7, in0 ;;88 and r14 = -8, r14 ;;89 cmp.eq p6, p7 = r14, in090 (p7) br.cond.dptk 0b91 shr.u r18 = in2, 3 ;;92 cmp.ne p6, p7 = 0, r1893 (p7) br.cond.dpnt 5f ;;94 (p6) adds r14 = -1, r1895 (p6) mov r16 = r096 (p6) mov r17 = r0 ;;97 (p6) mov ar.lc = r1498 99 4:100 101 shladd r14 = r16, 3, r0102 adds r16 = 1, r17 ;;103 add r15 = in1, r14104 add r14 = in0, r14105 mov r17 = r16 ;;106 ld8 r15 = [r15] ;;107 st8 [r14] = r15108 br.cloop.sptk.few 4b109 110 5:111 112 and r15 = 7, in2113 shladd r14 = r18, 3, r0114 mov r16 = r0115 mov r18 = r0 ;;116 cmp.eq p6, p7 = 0, r15117 add in0 = r14, in0118 adds r15 = -1, r15119 add r17 = r14, in1120 (p6) br.cond.dpnt 2b ;;121 mov ar.lc = r15122 123 6:124 125 add r14 = r16, r17126 add r15 = r16, in0127 adds r16 = 1, r18 ;;128 ld1 r14 = [r14]129 mov r18 = r16 ;;130 st1 [r15] = r14131 br.cloop.sptk.few 6b ;;132 mov ar.lc = r2133 mov ar.pfs = loc0134 br.ret.sptk.many rp135 136 121 memcpy_from_uspace_failover_address: 137 122 memcpy_to_uspace_failover_address: 138 /* Return 0 on failure */ 139 mov r8 = r0 123 mov r8 = r0 /* return 0 on failure */ 140 124 mov ar.pfs = loc0 141 125 br.ret.sptk.many rp … … 161 145 * @param in4 Value to be stored in IPSR. 162 146 * @param in5 Value to be stored in RSC. 163 *164 147 */ 165 148 .global switch_to_userspace 166 149 switch_to_userspace: 167 150 alloc loc0 = ar.pfs, 6, 3, 0, 0 168 169 /* Disable interruption collection and interrupts */ 170 rsm (PSR_IC_MASK | PSR_I_MASK) 151 rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ 171 152 srlz.d ;; 172 153 srlz.i ;; … … 175 156 mov cr.iip = in0 176 157 mov r12 = in1 177 158 178 159 xor r1 = r1, r1 179 160 … … 184 165 movl loc2 = PFM_MASK ;; 185 166 and loc1 = loc2, loc1 ;; 186 mov cr.ifs = loc1 ;; 187 167 mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ 168 188 169 invala 189 170 190 171 mov loc1 = ar.rsc ;; 191 and loc1 = ~3, loc1 ;; 192 mov ar.rsc = loc1 ;; 193 172 and loc1 = ~3, loc1 ;; 173 mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ 174 194 175 flushrs ;; 195 176 … … 200 181 201 182 rfi ;; 202 203 .global early_putchar204 early_putchar:205 br.ret.sptk.many b0
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