Changeset e8975278 in mainline for boot/arch/arm32/src/putchar.c
- Timestamp:
- 2018-05-10T15:14:02Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 1420cae9
- Parents:
- ae7d03c
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-10 07:53:56)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-10 15:14:02)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/putchar.c
rae7d03c re8975278 51 51 { 52 52 volatile uint32_t *thr = 53 53 (volatile uint32_t *) BBONE_SCONS_THR; 54 54 volatile uint32_t *ssr = 55 55 (volatile uint32_t *) BBONE_SCONS_SSR; 56 56 57 57 /* Wait until transmitter is empty */ 58 while (*ssr & BBONE_TXFIFO_FULL); 58 while (*ssr & BBONE_TXFIFO_FULL) 59 ; 59 60 60 61 /* Transmit byte */ … … 78 79 79 80 /* Wait until transmitter is empty. */ 80 while ((*ssr & BBXM_THR_FULL) == 1) ; 81 while ((*ssr & BBXM_THR_FULL) == 1) 82 ; 81 83 82 84 /* Transmit byte. */ … … 144 146 write32(BCM2835_UART0_FBRD, 40); /* Set fractional baud rate */ 145 147 write32(BCM2835_UART0_LCRH, 146 BCM2835_UART0_LCRH_FEN |/* Enable FIFOs */147 BCM2835_UART0_LCRH_WL8);/* Word length: 8 */148 BCM2835_UART0_LCRH_FEN | /* Enable FIFOs */ 149 BCM2835_UART0_LCRH_WL8); /* Word length: 8 */ 148 150 write32(BCM2835_UART0_CR, 149 BCM2835_UART0_CR_UARTEN |/* Enable UART */150 151 151 BCM2835_UART0_CR_UARTEN | /* Enable UART */ 152 BCM2835_UART0_CR_TXE | /* Enable TX */ 153 BCM2835_UART0_CR_RXE); /* Enable RX */ 152 154 } 153 155 … … 159 161 } 160 162 161 while (read32(BCM2835_UART0_FR) & BCM2835_UART0_FR_TXFF); 163 while (read32(BCM2835_UART0_FR) & BCM2835_UART0_FR_TXFF) 164 ; 162 165 163 166 write32(BCM2835_UART0_DR, byte);
Note:
See TracChangeset
for help on using the changeset viewer.