Changes in kernel/arch/amd64/src/asm.S [45f7449:e98f1c3e] in mainline
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kernel/arch/amd64/src/asm.S
r45f7449 re98f1c3e 27 27 */ 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/pm.h> 30 31 #include <arch/mm/page.h> 32 #include <arch/istate_struct.h> 33 #include <arch/kseg_struct.h> 34 #include <arch/cpu.h> 35 #include <arch/smp/apic.h> 31 36 32 37 .text 33 .global interrupt_handlers34 .global syscall_entry35 .global cpuid36 .global has_cpuid37 .global read_efer_flag38 .global set_efer_flag39 .global memcpy_from_uspace40 .global memcpy_to_uspace41 .global memcpy_from_uspace_failover_address42 .global memcpy_to_uspace_failover_address43 .global early_putchar44 38 45 39 #define MEMCPY_DST %rdi … … 63 57 * 64 58 */ 65 memcpy_from_uspace: 66 memcpy_to_uspace: 59 FUNCTION_BEGIN(memcpy_from_uspace) 60 FUNCTION_BEGIN(memcpy_to_uspace) 67 61 movq MEMCPY_DST, %rax 68 62 … … 80 74 0: 81 75 ret /* return MEMCPY_SRC, success */ 82 83 memcpy_from_uspace_failover_address: 84 memcpy_to_uspace_failover_address: 76 FUNCTION_END(memcpy_from_uspace) 77 FUNCTION_END(memcpy_to_uspace) 78 79 SYMBOL(memcpy_from_uspace_failover_address) 80 SYMBOL(memcpy_to_uspace_failover_address) 85 81 xorl %eax, %eax /* return 0, failure */ 86 82 ret … … 91 87 * 92 88 */ 93 has_cpuid: 89 FUNCTION_BEGIN(has_cpuid) 94 90 /* Load RFLAGS */ 95 91 pushfq … … 98 94 99 95 /* Flip the ID bit */ 100 btcl $21, %edx96 xorl $RFLAGS_ID, %edx 101 97 102 98 /* Store RFLAGS */ … … 107 103 /* Get the ID bit again */ 108 104 popq %rdx 109 andl $ (1 << 21), %eax110 andl $ (1 << 21), %edx105 andl $RFLAGS_ID, %eax 106 andl $RFLAGS_ID, %edx 111 107 112 108 /* 0 if not supported, 1 if supported */ 113 109 xorl %edx, %eax 114 110 ret 115 116 cpuid: 111 FUNCTION_END(has_cpuid) 112 113 FUNCTION_BEGIN(cpuid) 117 114 /* Preserve %rbx across function calls */ 118 115 movq %rbx, %r10 … … 129 126 movq %r10, %rbx 130 127 ret 131 132 set_efer_flag: 133 movl $0xc0000080, %ecx 128 FUNCTION_END(cpuid) 129 130 /** Enable local APIC 131 * 132 * Enable local APIC in MSR. 133 * 134 */ 135 FUNCTION_BEGIN(enable_l_apic_in_msr) 136 movl $AMD_MSR_APIC_BASE, %ecx 134 137 rdmsr 135 btsl %edi, %eax138 orl $(L_APIC_BASE | AMD_APIC_BASE_GE), %eax 136 139 wrmsr 137 140 ret 138 139 read_efer_flag: 140 movl $0xc0000080, %ecx 141 rdmsr 142 ret 143 144 #define ISTATE_OFFSET_RAX 0 145 #define ISTATE_OFFSET_RBX 8 146 #define ISTATE_OFFSET_RCX 16 147 #define ISTATE_OFFSET_RDX 24 148 #define ISTATE_OFFSET_RSI 32 149 #define ISTATE_OFFSET_RDI 40 150 #define ISTATE_OFFSET_RBP 48 151 #define ISTATE_OFFSET_R8 56 152 #define ISTATE_OFFSET_R9 64 153 #define ISTATE_OFFSET_R10 72 154 #define ISTATE_OFFSET_R11 80 155 #define ISTATE_OFFSET_R12 88 156 #define ISTATE_OFFSET_R13 96 157 #define ISTATE_OFFSET_R14 104 158 #define ISTATE_OFFSET_R15 112 159 #define ISTATE_OFFSET_ALIGNMENT 120 160 #define ISTATE_OFFSET_RBP_FRAME 128 161 #define ISTATE_OFFSET_RIP_FRAME 136 162 #define ISTATE_OFFSET_ERROR_WORD 144 163 #define ISTATE_OFFSET_RIP 152 164 #define ISTATE_OFFSET_CS 160 165 #define ISTATE_OFFSET_RFLAGS 168 166 #define ISTATE_OFFSET_RSP 176 167 #define ISTATE_OFFSET_SS 184 141 FUNCTION_END(enable_l_apic_in_msr) 168 142 169 143 /* … … 171 145 * error word. 172 146 */ 173 #define ISTATE_SOFT_SIZE 144147 #define ISTATE_SOFT_SIZE ISTATE_SIZE - (6 * 8) 174 148 175 149 /** … … 181 155 182 156 .macro handler i 183 .global int_\i 184 int_\i: 157 SYMBOL(int_\i) 185 158 186 159 /* … … 228 201 229 202 /* 203 * Is this trap from the kernel? 204 */ 205 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 206 jz 0f 207 208 /* 209 * Switch to kernel FS base. 210 */ 211 swapgs 212 movl $AMD_MSR_FS, %ecx 213 movl %gs:KSEG_OFFSET_FSBASE, %eax 214 movl %gs:KSEG_OFFSET_FSBASE+4, %edx 215 wrmsr 216 swapgs 217 218 /* 230 219 * Imitate a regular stack frame linkage. 231 220 * Stop stack traces here if we came from userspace. 232 221 */ 233 xorl %edx, %edx 234 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 222 0: movl $0x0, %edx 235 223 cmovnzq %rdx, %rbp 236 224 … … 273 261 53,54,55,56,57,58,59,60,61,62,63 274 262 275 interrupt_handlers: 263 SYMBOL(interrupt_handlers) 276 264 .irp cnt, LIST_0_63 277 265 handler \cnt … … 297 285 * 298 286 */ 299 syscall_entry: 287 SYMBOL(syscall_entry) 300 288 /* Switch to hidden %gs */ 301 289 swapgs 302 290 303 /* 304 * %gs:0 Scratch space for this thread's user RSP 305 * %gs:8 Address to be used as this thread's kernel RSP 306 */ 307 308 movq %rsp, %gs:0 /* save this thread's user RSP */ 309 movq %gs:8, %rsp /* set this thread's kernel RSP */ 310 291 movq %rsp, %gs:KSEG_OFFSET_USTACK_RSP /* save this thread's user RSP */ 292 movq %gs:KSEG_OFFSET_KSTACK_RSP, %rsp /* set this thread's kernel RSP */ 293 311 294 /* 312 295 * Note that the space needed for the imitated istate structure has been … … 337 320 338 321 /* 322 * Switch to kernel FS base. 323 */ 324 movl $AMD_MSR_FS, %ecx 325 movl %gs:KSEG_OFFSET_FSBASE, %eax 326 movl %gs:KSEG_OFFSET_FSBASE+4, %edx 327 wrmsr 328 movq ISTATE_OFFSET_RDX(%rsp), %rdx /* restore 3rd argument */ 329 330 /* 339 331 * Save the return address and the userspace stack on locations that 340 332 * would normally be taken by them. 341 333 */ 342 movq %gs: 0, %rax334 movq %gs:KSEG_OFFSET_USTACK_RSP, %rax 343 335 movq %rax, ISTATE_OFFSET_RSP(%rsp) 344 336 movq %rcx, ISTATE_OFFSET_RIP(%rsp) … … 420 412 * 421 413 */ 422 early_putchar: 423 414 FUNCTION_BEGIN(early_putchar) 424 415 #if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) 425 416 … … 549 540 550 541 ret 551 542 FUNCTION_END(early_putchar)
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