Changes in uspace/drv/block/ahci/ahci_hw.h [730dce77:eb3683a] in mainline
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uspace/drv/block/ahci/ahci_hw.h (modified) (20 diffs)
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uspace/drv/block/ahci/ahci_hw.h
r730dce77 reb3683a 35 35 36 36 #include <sys/types.h> 37 38 /*----------------------------------------------------------------------------*/ 39 /*-- AHCI standard constants -------------------------------------------------*/ 40 /*----------------------------------------------------------------------------*/ 41 42 /** AHCI standard 1.3 - maximum ports. */ 43 #define AHCI_MAX_PORTS 32 37 44 38 45 /*----------------------------------------------------------------------------*/ … … 198 205 typedef union { 199 206 struct { 200 207 /** Header layout. */ 201 208 unsigned int hl : 7; 202 /** Multi function device . */209 /** Multi function device flag. */ 203 210 unsigned int mfd : 1; 204 211 }; … … 281 288 typedef struct 282 289 { 283 /** Indicates the minimum grant time (in ? microseconds)284 * that the devicewishes grant asserted.290 /** Indicates the minimum grant time that the device 291 * wishes grant asserted. 285 292 */ 286 293 uint8_t u8; … … 297 304 /*-- AHCI Memory Registers ---------------------------------------------------*/ 298 305 /*----------------------------------------------------------------------------*/ 306 307 /** Number of pages for ahci memory registers. */ 308 #define AHCI_MEMREGS_PAGES_COUNT 8 299 309 300 310 /** AHCI Memory register Generic Host Control - HBA Capabilities. */ … … 371 381 372 382 /** AHCI Memory register Interrupt pending register. */ 373 typedef struct { 374 /** Interrupt pending status, if set, indicates that 375 * the corresponding port has an interrupt pending. 376 */ 377 uint32_t u32; 378 } ahci_ghc_is_t; 383 typedef uint32_t ahci_ghc_is_t; 384 385 /** AHCI GHC register offset. */ 386 #define AHCI_GHC_IS_REGISTER_OFFSET 2 387 388 /** AHCI ports registers offset. */ 389 #define AHCI_PORTS_REGISTERS_OFFSET 64 390 391 /** AHCI port registers size. */ 392 #define AHCI_PORT_REGISTERS_SIZE 32 393 394 /** AHCI port IS register offset. */ 395 #define AHCI_PORT_IS_REGISTER_OFFSET 4 379 396 380 397 /** AHCI Memory register Ports implemented. */ … … 427 444 /** Size of the transmit message buffer area in dwords. */ 428 445 uint16_t sz; 429 /* Offset of the transmit message buffer area in dwords 446 /* 447 * Offset of the transmit message buffer area in dwords 430 448 * from the beginning of ABAR 431 449 */ … … 462 480 /** Activity LED hardware driven. */ 463 481 unsigned int alhd : 1; 464 /** port multiplier support. */482 /** Port multiplier support. */ 465 483 unsigned int pm : 1; 466 484 /** Reserved. */ … … 509 527 typedef struct 510 528 { 511 /** Host Capabilities .*/529 /** Host Capabilities */ 512 530 uint32_t cap; 513 /** Global Host Control .*/531 /** Global Host Control */ 514 532 uint32_t ghc; 515 /** Interrupt Status .*/516 uint32_t is;517 /** Ports Implemented .*/533 /** Interrupt Status */ 534 ahci_ghc_is_t is; 535 /** Ports Implemented */ 518 536 uint32_t pi; 519 /** Version .*/537 /** Version */ 520 538 uint32_t vs; 521 /** Command Completion Coalescing Control .*/539 /** Command Completion Coalescing Control */ 522 540 uint32_t ccc_ctl; 523 /** Command Completion Coal secing Ports.*/541 /** Command Completion Coalescing Ports */ 524 542 uint32_t ccc_ports; 525 /** Enclosure Management Location .*/543 /** Enclosure Management Location */ 526 544 uint32_t em_loc; 527 /** Enclosure Management Control .*/545 /** Enclosure Management Control */ 528 546 uint32_t em_ctl; 529 /** Host Capabilities Extended .*/547 /** Host Capabilities Extended */ 530 548 uint32_t cap2; 531 /** BIOS/OS Handoff Control and Status .*/549 /** BIOS/OS Handoff Control and Status */ 532 550 uint32_t bohc; 533 551 } ahci_ghc_t; … … 586 604 587 605 /** AHCI Memory register Port x Interrupt Status. */ 588 typedef union { 589 struct { 590 /** Device to Host Register FIS Interrupt. */ 591 unsigned int dhrs : 1; 592 /** PIO Setup FIS Interrupt. */ 593 unsigned int pss : 1; 594 /** DMA Setup FIS Interrupt. */ 595 unsigned int dss : 1; 596 /** Set Device Bits Interrupt. */ 597 unsigned int sdbs : 1; 598 /** Unknown FIS Interrupt. */ 599 unsigned int ufs : 1; 600 /** Descriptor Processed. */ 601 unsigned int dps : 1; 602 /** Port Connect Change Status. */ 603 unsigned int pcs : 1; 604 /** Device Mechanical Presence Status. */ 605 unsigned int dmps : 1; 606 /** Reserved. */ 607 unsigned int reserved1 : 14; 608 /** PhyRdy Change Status. */ 609 unsigned int prcs : 1; 610 /** Incorrect Port Multiplier Status. */ 611 unsigned int ipms : 1; 612 /** Overflow Status. */ 613 unsigned int ofs : 1; 614 /** Reserved. */ 615 unsigned int reserved2 : 1; 616 /** Interface Non-fatal Error Status. */ 617 unsigned int infs : 1; 618 /** Interface Fatal Error Status. */ 619 unsigned int ifs : 1; 620 /** Host Bus Data Error Status. */ 621 unsigned int hbds : 1; 622 /** Host Bus Fatal Error Status. */ 623 unsigned int hbfs : 1; 624 /** Task File Error Status. */ 625 unsigned int tfes : 1; 626 /** Cold Port Detect Status. */ 627 unsigned int cpds : 1; 628 }; 629 uint32_t u32; 630 } ahci_port_is_t; 606 typedef uint32_t ahci_port_is_t; 631 607 632 608 #define AHCI_PORT_IS_DHRS (1 << 0) … … 683 659 static inline int ahci_port_is_end_of_operation(ahci_port_is_t port_is) 684 660 { 685 return port_is .u32& AHCI_PORT_END_OF_OPERATION;661 return port_is & AHCI_PORT_END_OF_OPERATION; 686 662 } 687 663 … … 695 671 static inline int ahci_port_is_error(ahci_port_is_t port_is) 696 672 { 697 return port_is .u32& AHCI_PORT_IS_ERROR;673 return port_is & AHCI_PORT_IS_ERROR; 698 674 } 699 675 … … 707 683 static inline int ahci_port_is_permanent_error(ahci_port_is_t port_is) 708 684 { 709 return port_is .u32& AHCI_PORT_IS_PERMANENT_ERROR;685 return port_is & AHCI_PORT_IS_PERMANENT_ERROR; 710 686 } 711 687 … … 719 695 static inline int ahci_port_is_tfes(ahci_port_is_t port_is) 720 696 { 721 return port_is .u32& AHCI_PORT_IS_TFES;697 return port_is & AHCI_PORT_IS_TFES; 722 698 } 723 699 … … 817 793 * Values: 818 794 * 7h - fh Reserved, 819 * 6h Slumber - This shall cause the HBA to request a transition of the820 * 795 * 6h Slumber - This shall cause the HBA to request a transition 796 * of the interface to the Slumber state, 821 797 * 3h - 5h Reserved, 822 * 2h Partial - This shall cause the HBA to request a transition of the823 * 798 * 2h Partial - This shall cause the HBA to request a transition 799 * of the interface to the Partial state, 824 800 * 1h Active, 825 801 * 0h No-Op / Idle. … … 856 832 /** LBA Mid Register */ 857 833 uint8_t lba_mr; 858 /** 834 /** LBA High Register */ 859 835 uint8_t lba_hr; 860 836 }; … … 876 852 uint32_t u32; 877 853 } ahci_port_ssts_t; 854 855 /** Device detection active status. */ 856 #define AHCI_PORT_SSTS_DET_ACTIVE 3 878 857 879 858 /** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */ … … 974 953 uint32_t pxfbu; 975 954 /** Port x Interrupt Status. */ 976 uint32_t pxis;955 ahci_port_is_t pxis; 977 956 /** Port x Interrupt Enable. */ 978 957 uint32_t pxie; … … 1010 989 ahci_ghc_t ghc; 1011 990 /** Reserved. */ 1012 uint 8_t reserved[52];991 uint32_t reserved[13]; 1013 992 /** Reserved for NVMHCI. */ 1014 uint 8_t reservedfornvmhci[64];993 uint32_t reservedfornvmhci[16]; 1015 994 /** Vendor Specific registers. */ 1016 uint 8_t vendorspecificsregs[96];995 uint32_t vendorspecificsregs[24]; 1017 996 /** Ports. */ 1018 ahci_port_t ports[ 32];997 ahci_port_t ports[AHCI_MAX_PORTS]; 1019 998 } ahci_memregs_t; 1020 999 1021 /** AHCI Command header entry. */ 1000 /** AHCI Command header entry. 1001 * 1002 * This structure is not an AHCI register. 1003 * 1004 */ 1022 1005 typedef volatile struct { 1023 1006 /** Flags. */ … … 1033 1016 } ahci_cmdhdr_t; 1034 1017 1035 /** AHCI Command Physical Region Descriptor entry. */ 1018 /** Clear Busy upon R_OK (C) flag. */ 1019 #define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK 0x0400 1020 1021 /** Write operation flag. */ 1022 #define AHCI_CMDHDR_FLAGS_WRITE 0x0040 1023 1024 /** 2 DW length command flag. */ 1025 #define AHCI_CMDHDR_FLAGS_2DWCMD 0x0002 1026 1027 /** 5 DW length command flag. */ 1028 #define AHCI_CMDHDR_FLAGS_5DWCMD 0x0005 1029 1030 /** AHCI Command Physical Region Descriptor entry. 1031 * 1032 * This structure is not an AHCI register. 1033 * 1034 */ 1036 1035 typedef volatile struct { 1037 1036 /** Word aligned 32-bit data base address. */ … … 1045 1044 /** Reserved */ 1046 1045 unsigned int reserved2 : 9; 1047 /** Interrupton completion */1046 /** Set Interrupt on each operation completion */ 1048 1047 unsigned int ioc : 1; 1049 1048 } ahci_cmd_prdt_t;
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