Changeset ed166f7 in mainline for kernel/arch/sparc64/include/trap/mmu.h

Timestamp:

2006-08-31T18:53:14Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6767c1d

Parents:

e0b241f

Message:

A lot of untested sparc64 stuff:

• Write ASID to hardware when a thread is about to run in userspace.
• Add userspace() and switch_to_userspace() functions.
• Handle special cases when the userspace spill/fill handler causes MMU trap.
• Resolve some TODOs in the existing sparc64 code.
• sparc64 has now C99 compliant header guards.
• Formatting and indentation fixes.

File:

• kernel/arch/sparc64/include/trap/mmu.h (modified) (6 diffs)

kernel/arch/sparc64/include/trap/mmu.h

@@ -43 +43 @@
 #include <arch/mm/mmu.h>
 #include <arch/mm/tte.h>
+#include <arch/trap/regwin.h>
 
 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS     0x64
@@ -51 +52 @@
 
 #ifdef __ASM__
+
 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
-        /*
-         * First, try to refill TLB from TSB.
-         */
+        !
+        ! First, try to refill TLB from TSB.
+        !
         ! TODO
 
@@ -75 +77 @@
          * Note that branch-delay slots are used in order to save space.
          */
-0:
+
         mov VA_DMMU_TAG_ACCESS, %g1
         ldxa [%g1] ASI_DMMU, %g1                        ! read the faulting Context and VPN
@@ -85 +87 @@
 
         or %g3, (TTE_CP|TTE_P|TTE_W), %g2               ! 8K pages are the default (encoded as 0)
-        set 1, %g3
-        sllx %g3, TTE_V_SHIFT, %g3
-        or %g2, %g3, %g2
+        mov 1, %g3
+        sllx %g3, TTE_V_SHIFT, %g3
+        or %g2, %g3, %g2
         stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
         retry
@@ -93 +95 @@
         /*
          * Third, catch and handle special cases when the trap is caused by
-         * some register window trap handler.
+         * the userspace register window spill or fill handler. In case
+         * one of these two traps caused this trap, we just lower the trap
+         * level and service the DTLB miss. In the end, we restart
+         * the offending SAVE or RESTORE.
          */
 0:
-        ! TODO
+        HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
 
-0:
         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
@@ -104 +108 @@
 
 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER
+        /*
+         * First, try to refill TLB from TSB.
+         */
+        ! TODO
+
+        /*
+         * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
+         */
+        HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
+
         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
         PREEMPTIBLE_HANDLER fast_data_access_protection
 .endm
+
+/*
+ * Macro used to lower TL when a MMU trap is caused by
+ * the userspace register window spill or fill handler.
+ */
+.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
+        rdpr %tl, %g1
+        dec %g1
+        brz %g1, 0f                     ! if TL was 1, skip
+        nop
+        wrpr %g1, 0, %tl                ! TL--
+        rdpr %tt, %g2
+        cmp %g2, TT_SPILL_1_NORMAL
+        be 0f                           ! trap from spill_1_normal
+        cmp %g2, TT_FILL_1_NORMAL
+        be 0f                           ! trap from fill_1_normal
+        inc %g1
+        wrpr %g1, 0, %tl                ! another trap, TL++
+0:
+.endm
+
 #endif /* __ASM__ */