Changeset ee06f2a in mainline for kernel/arch/ia32/src/drivers/i8259.c


Ignore:
Timestamp:
2009-02-15T15:28:00Z (16 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
2d96f4d
Parents:
e7f2ad68
Message:

Introduce a more platform-neutral name for programmed I/O.

The new API looks like pio_read_n() or pio_write_n(), where n is 8, 16 or 32.
The old API (i.e. inb(), inw(), inl(), outb() outw(), outl()) may have made
some people think that the interface is only to be used with the separate I/O
space. That's not the case. This API is to be implemented on all platforms
so that we can finally have really generic kernel device drivers.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/src/drivers/i8259.c

    re7f2ad68 ree06f2a  
    5050{
    5151        /* ICW1: this is ICW1, ICW4 to follow */
    52         outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
     52        pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
    5353
    5454        /* ICW2: IRQ 0 maps to INT IRQBASE */
    55         outb(PIC_PIC0PORT2, IVT_IRQBASE);
     55        pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE);
    5656
    5757        /* ICW3: pic1 using IRQ IRQ_PIC1 */
    58         outb(PIC_PIC0PORT2, 1 << IRQ_PIC1);
     58        pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1);
    5959
    6060        /* ICW4: i8086 mode */
    61         outb(PIC_PIC0PORT2, 1);
     61        pio_write_8(PIC_PIC0PORT2, 1);
    6262
    6363        /* ICW1: ICW1, ICW4 to follow */
    64         outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
     64        pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
    6565
    6666        /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
    67         outb(PIC_PIC1PORT2, IVT_IRQBASE + 8);
     67        pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8);
    6868
    6969        /* ICW3: pic1 is known as IRQ_PIC1 */
    70         outb(PIC_PIC1PORT2, IRQ_PIC1);
     70        pio_write_8(PIC_PIC1PORT2, IRQ_PIC1);
    7171
    7272        /* ICW4: i8086 mode */
    73         outb(PIC_PIC1PORT2, 1);
     73        pio_write_8(PIC_PIC1PORT2, 1);
    7474
    7575        /*
     
    9595
    9696        if (irqmask & 0xff) {
    97                 x = inb(PIC_PIC0PORT2);
    98                 outb(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
     97                x = pio_read_8(PIC_PIC0PORT2);
     98                pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
    9999        }
    100100        if (irqmask >> 8) {
    101                 x = inb(PIC_PIC1PORT2);
    102                 outb(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
     101                x = pio_read_8(PIC_PIC1PORT2);
     102                pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
    103103        }
    104104}
     
    109109
    110110        if (irqmask & 0xff) {
    111                 x = inb(PIC_PIC0PORT2);
    112                 outb(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
     111                x = pio_read_8(PIC_PIC0PORT2);
     112                pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
    113113        }
    114114        if (irqmask >> 8) {
    115                 x = inb(PIC_PIC1PORT2);
    116                 outb(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
     115                x = pio_read_8(PIC_PIC1PORT2);
     116                pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
    117117        }
    118118}
     
    120120void pic_eoi(void)
    121121{
    122         outb(0x20, 0x20);
    123         outb(0xa0, 0x20);
     122        pio_write_8(0x20, 0x20);
     123        pio_write_8(0xa0, 0x20);
    124124}
    125125
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