Changeset f24d300 in mainline for kernel/arch/amd64/src/fpu_context.c
- Timestamp:
- 2009-03-03T15:52:55Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e762b43
- Parents:
- add04f7
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/fpu_context.c
radd04f7 rf24d300 40 40 { 41 41 asm volatile ( 42 "fxsave % 0"43 : "=m"(*fctx)44 42 "fxsave %[fctx]\n" 43 : [fctx] "=m" (*fctx) 44 ); 45 45 } 46 46 … … 49 49 { 50 50 asm volatile ( 51 "fxrstor % 0"52 : "=m"(*fctx)53 51 "fxrstor %[fctx]\n" 52 : [fctx] "=m" (*fctx) 53 ); 54 54 } 55 55 … … 58 58 /* TODO: Zero all SSE, MMX etc. registers */ 59 59 asm volatile ( 60 "fninit ;"60 "fninit\n" 61 61 ); 62 62 }
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