Changeset f2ea5d8 in mainline for kernel/arch/sparc64/include/trap/mmu.h

Timestamp:

2006-11-17T20:21:25Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f18cc64

Parents:

282f2c9c

Message:

sparc64 code to support physical memory that starts on non-zero addresses.
Still needs to be tested on systems with such setup.

File:

• kernel/arch/sparc64/include/trap/mmu.h (modified) (1 diff)

kernel/arch/sparc64/include/trap/mmu.h

@@ -112 +112 @@
         bz 0f                                           ! page address is zero
 
-        or %g3, (TTE_CV|TTE_CP|TTE_P|TTE_W), %g2        ! 8K pages are the default (encoded as 0)
-        mov 1, %g3
-        sllx %g3, TTE_V_SHIFT, %g3
-        or %g2, %g3, %g2
+        sethi %hi(kernel_8k_tlb_data_template), %g2
+        ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
+        or %g3, %g2, %g2
         stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
         retry