Changes in kernel/arch/ppc32/include/mm/page.h [b8230b9:f3277d49] in mainline
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kernel/arch/ppc32/include/mm/page.h
rb8230b9 rf3277d49 27 27 */ 28 28 29 /** @addtogroup ppc32mm 29 /** @addtogroup ppc32mm 30 30 * @{ 31 31 */ … … 38 38 #include <arch/mm/frame.h> 39 39 40 #define PAGE_WIDTH 41 #define PAGE_SIZE 40 #define PAGE_WIDTH FRAME_WIDTH 41 #define PAGE_SIZE FRAME_SIZE 42 42 43 43 #ifdef KERNEL 44 44 45 45 #ifndef __ASM__ 46 #define KA2PA(x)(((uintptr_t) (x)) - 0x80000000)47 #define PA2KA(x)(((uintptr_t) (x)) + 0x80000000)46 # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) 47 # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) 48 48 #else 49 #define KA2PA(x)((x) - 0x80000000)50 #define PA2KA(x)((x) + 0x80000000)49 # define KA2PA(x) ((x) - 0x80000000) 50 # define PA2KA(x) ((x) + 0x80000000) 51 51 #endif 52 52 … … 65 65 66 66 /* Number of entries in each level. */ 67 #define PTL0_ENTRIES_ARCH 68 #define PTL1_ENTRIES_ARCH 69 #define PTL2_ENTRIES_ARCH 70 #define PTL3_ENTRIES_ARCH 67 #define PTL0_ENTRIES_ARCH 1024 68 #define PTL1_ENTRIES_ARCH 0 69 #define PTL2_ENTRIES_ARCH 0 70 #define PTL3_ENTRIES_ARCH 1024 71 71 72 72 /* Page table sizes for each level. */ 73 #define PTL0_SIZE_ARCH 74 #define PTL1_SIZE_ARCH 75 #define PTL2_SIZE_ARCH 76 #define PTL3_SIZE_ARCH 73 #define PTL0_SIZE_ARCH ONE_FRAME 74 #define PTL1_SIZE_ARCH 0 75 #define PTL2_SIZE_ARCH 0 76 #define PTL3_SIZE_ARCH ONE_FRAME 77 77 78 78 /* Macros calculating indices into page tables on each level. */ 79 #define PTL0_INDEX_ARCH(vaddr) 80 #define PTL1_INDEX_ARCH(vaddr) 81 #define PTL2_INDEX_ARCH(vaddr) 82 #define PTL3_INDEX_ARCH(vaddr) 79 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) 80 #define PTL1_INDEX_ARCH(vaddr) 0 81 #define PTL2_INDEX_ARCH(vaddr) 0 82 #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) 83 83 84 84 /* Get PTE address accessors for each level. */ 85 85 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ 86 86 (((pte_t *) (ptl0))[(i)].pfn << 12) 87 88 87 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ 89 88 (ptl1) 90 91 89 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ 92 90 (ptl2) 93 94 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ 91 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ 95 92 (((pte_t *) (ptl3))[(i)].pfn << 12) 96 93 97 94 /* Set PTE address accessors for each level. */ 98 95 #define SET_PTL0_ADDRESS_ARCH(ptl0) 99 100 96 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ 101 97 (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) 102 103 98 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) 104 99 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) 105 106 100 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ 107 101 (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) … … 110 104 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ 111 105 get_pt_flags((pte_t *) (ptl0), (size_t) (i)) 112 113 106 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ 114 107 PAGE_PRESENT 115 116 108 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ 117 109 PAGE_PRESENT 118 119 110 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ 120 111 get_pt_flags((pte_t *) (ptl3), (size_t) (i)) 121 112 122 113 /* Set PTE flags accessors for each level. */ 123 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) 114 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ 124 115 set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x)) 125 126 116 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) 127 117 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) 128 129 118 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 130 119 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) 131 120 132 121 /* Macros for querying the last-level PTEs. */ 133 #define PTE_VALID_ARCH(pte) 134 #define PTE_PRESENT_ARCH(pte) 135 #define PTE_GET_FRAME_ARCH(pte) 136 #define PTE_WRITABLE_ARCH(pte) 137 #define PTE_EXECUTABLE_ARCH(pte) 122 #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) 123 #define PTE_PRESENT_ARCH(pte) ((pte)->present != 0) 124 #define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn << 12) 125 #define PTE_WRITABLE_ARCH(pte) 1 126 #define PTE_EXECUTABLE_ARCH(pte) 1 138 127 139 128 #ifndef __ASM__ … … 144 133 /** Page Table Entry. */ 145 134 typedef struct { 146 unsigned intpresent : 1; /**< Present bit. */147 unsigned intpage_write_through : 1; /**< Write thought caching. */148 unsigned intpage_cache_disable : 1; /**< No caching. */149 unsigned intaccessed : 1; /**< Accessed bit. */150 unsigned intglobal : 1; /**< Global bit. */151 unsigned intvalid : 1; /**< Valid content even if not present. */152 unsigned intpfn : 20; /**< Physical frame number. */135 unsigned present : 1; /**< Present bit. */ 136 unsigned page_write_through : 1; /**< Write thought caching. */ 137 unsigned page_cache_disable : 1; /**< No caching. */ 138 unsigned accessed : 1; /**< Accessed bit. */ 139 unsigned global : 1; /**< Global bit. */ 140 unsigned valid : 1; /**< Valid content even if not present. */ 141 unsigned pfn : 20; /**< Physical frame number. */ 153 142 } pte_t; 154 143 155 144 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 156 145 { 157 pte_t * entry= &pt[i];146 pte_t *p = &pt[i]; 158 147 159 return (((! entry->page_cache_disable) << PAGE_CACHEABLE_SHIFT) |160 ((! entry->present) << PAGE_PRESENT_SHIFT) |148 return (((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT) | 149 ((!p->present) << PAGE_PRESENT_SHIFT) | 161 150 (1 << PAGE_USER_SHIFT) | 162 151 (1 << PAGE_READ_SHIFT) | 163 152 (1 << PAGE_WRITE_SHIFT) | 164 153 (1 << PAGE_EXEC_SHIFT) | 165 ( entry->global << PAGE_GLOBAL_SHIFT));154 (p->global << PAGE_GLOBAL_SHIFT)); 166 155 } 167 156 168 157 static inline void set_pt_flags(pte_t *pt, size_t i, int flags) 169 158 { 170 pte_t * entry= &pt[i];159 pte_t *p = &pt[i]; 171 160 172 entry->page_cache_disable = !(flags & PAGE_CACHEABLE);173 entry->present = !(flags & PAGE_NOT_PRESENT);174 entry->global = (flags & PAGE_GLOBAL) != 0;175 entry->valid = 1;161 p->page_cache_disable = !(flags & PAGE_CACHEABLE); 162 p->present = !(flags & PAGE_NOT_PRESENT); 163 p->global = (flags & PAGE_GLOBAL) != 0; 164 p->valid = 1; 176 165 } 177 166
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