Changes in / [a940f1d:f3386d7] in mainline


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Files:
2 added
8 edited

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  • boot/arch/arm32/src/asm.S

    ra940f1d rf3386d7  
    7171        mrc     p15, 0, r4, c1, c0, 0
    7272        bic     r4, r4, #(1 << CP15_C1_DC)
     73#ifndef PROCESSOR_ARCH_armv7_a
    7374        bic     r4, r4, #(1 << CP15_C1_IC)
    7475        bic     r4, r4, #(1 << CP15_C1_BP)
     76#endif
    7577        mcr     p15, 0, r4, c1, c0, 0
    7678

  • boot/arch/arm32/src/main.c

    ra940f1d rf3386d7  
    6363{
    6464        const uintptr_t addr = (uintptr_t)address;
    65         /* DCIMVAC - invalidate by address to the point of coherence */
    6665        for (uintptr_t a = addr; a < addr + size; a += 4) {
     66                /* DCIMVAC - invalidate by address to the point of coherence */
    6767                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
    6868        }
    … …  
    7272{
    7373        const uintptr_t addr = (uintptr_t)address;
    74         /* DCCMVAC - clean by address to the point of coherence */
    7574        for (uintptr_t a = addr; a < addr + size; a += 4) {
     75                /* DCCMVAC - clean by address to the point of coherence */
    7676                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
    7777        }
    … …  
    8282void bootstrap(void)
    8383{
    84         /* Make sure  we run in memory code when caches are enabled,
     84        /* Make sure we run in memory code when caches are enabled,
    8585         * make sure we read memory data too. This part is ARMv7 specific as
    8686         * ARMv7 no longer invalidates caches on restart.
    … …  
    105105                    components[i].start, components[i].name, components[i].inflated,
    106106                    components[i].size);
     107                /* Make sure there is no cache garbage in read locations */
    107108                invalidate_dcache(components[i].start, components[i].size);
    108109        }
    … …  
    148149                        halt();
    149150                }
     151                /* Make sure data are in the memory, ICache will need them */
    150152                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    151153        }

  • kernel/arch/arm32/include/arch/asm.h

    ra940f1d rf3386d7  
    3838
    3939#include <typedefs.h>
     40#include <arch/cp15.h>
    4041#include <arch/stack.h>
    4142#include <config.h>
    … …  
    5152 * chapter 2.3.8 p.2-22 (52 in the PDF)
    5253 *
    53  * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
    54  * reference manual for armv4/5 CP15 implementation is mandatory only for
    55  * armv6+.
     54 * @note Although CP15WFI (mcr p15, 0, R0, c7, c0, 4) is defined in ARM
     55 * Architecture reference manual for armv4/5, CP15 implementation is mandatory
     56 * only for armv6+.
    5657 */
    5758NO_TRACE static inline void cpu_sleep(void)
    … …  
    6061        asm volatile ( "wfe" );
    6162#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
    62         asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
     63        WFI_write(0);
    6364#endif
    6465}

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    ra940f1d rf3386d7  
    4141#error "Do not include arch specific page.h directly use generic page.h instead"
    4242#endif
     43
     44#include <arch/cp15.h>
    4345
    4446/* Macros for querying the last-level PTE entries. */
    … …  
    128130NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    129131{
    130         asm volatile (
    131                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    132                 :: [pt] "r" (pt)
    133         );
     132        TTBR0_write((uint32_t)pt);
    134133}
    135134
    … …  
    223222       
    224223        /* default access permission */
    225         p->access_permission_0 = p->access_permission_1 = 
     224        p->access_permission_0 = p->access_permission_1 =
    226225            p->access_permission_2 = p->access_permission_3 =
    227226            PTE_AP_USER_NO_KERNEL_RW;
    … …  
    229228        if (flags & PAGE_USER)  {
    230229                if (flags & PAGE_READ) {
    231                         p->access_permission_0 = p->access_permission_1 = 
    232                             p->access_permission_2 = p->access_permission_3 = 
     230                        p->access_permission_0 = p->access_permission_1 =
     231                            p->access_permission_2 = p->access_permission_3 =
    233232                            PTE_AP_USER_RO_KERNEL_RW;
    234233                }
    235234                if (flags & PAGE_WRITE) {
    236                         p->access_permission_0 = p->access_permission_1 = 
    237                             p->access_permission_2 = p->access_permission_3 = 
    238                             PTE_AP_USER_RW_KERNEL_RW; 
     235                        p->access_permission_0 = p->access_permission_1 =
     236                            p->access_permission_2 = p->access_permission_3 =
     237                            PTE_AP_USER_RW_KERNEL_RW;
    239238                }
    240239        }

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    ra940f1d rf3386d7  
    4040#error "Do not include arch specific page.h directly use generic page.h instead"
    4141#endif
     42
     43#include <arch/cp15.h>
    4244
    4345/* Macros for querying the last-level PTE entries. */
    … …  
    132134NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    133135{
    134         asm volatile (
    135                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    136                 :: [pt] "r" (pt)
    137         );
     136        TTBR0_write((uint32_t)pt);
    138137}
    139138

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    ra940f1d rf3386d7  
    8585static void bb_timer_irq_handler(irq_t *irq)
    8686{
     87        amdm37x_gpt_irq_ack(&beagleboard.timer);
     88
    8789        /*
    8890         * We are holding a lock which prevents preemption.
    8991         * Release the lock, call clock() and reacquire the lock again.
    9092         */
    91         amdm37x_gpt_irq_ack(&beagleboard.timer);
    9293        spinlock_unlock(&irq->lock);
    9394        clock();
    … …  
    147148{
    148149        const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
    149         amdm37x_irc_irq_ack(beagleboard.irc_addr);
    150150
    151151        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    159159                    CPU->id, inum);
    160160        }
     161        /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
     162         * of ISR. DO this to avoid strange behavior. */
     163        amdm37x_irc_irq_ack(beagleboard.irc_addr);
    161164}
    162165

  • kernel/arch/arm32/src/mm/tlb.c

    ra940f1d rf3386d7  
    3737#include <arch/mm/asid.h>
    3838#include <arch/asm.h>
     39#include <arch/cp15.h>
    3940#include <typedefs.h>
    4041#include <arch/mm/page.h>
    … …  
    4647void tlb_invalidate_all(void)
    4748{
    48         asm volatile (
    49                 "eor r1, r1\n"
    50                 "mcr p15, 0, r1, c8, c7, 0\n"
    51                 ::: "r1"
    52         );
     49        TLBIALL_write(0);
    5350}
    5451
    … …  
    6057{
    6158        tlb_invalidate_all();
     59        // TODO: why not TLBIASID_write(asid) ?
    6260}
    6361
    … …  
    6563 *
    6664 * @param page Virtual adress of the page
    67  */ 
     65 */
    6866static inline void invalidate_page(uintptr_t page)
    6967{
    70         asm volatile (
    71                 "mcr p15, 0, %[page], c8, c7, 1\n"
    72                 :: [page] "r" (page)
    73         );
     68        TLBIMVA_write(page);
     69        //TODO: What about TLBIMVAA?
    7470}
    7571

  • kernel/genarch/include/genarch/drivers/amdm37x/gpt.h

    ra940f1d rf3386d7  
    3939#include <typedefs.h>
    4040#include <mm/km.h>
     41#include <time/clock.h>
    4142
    4243/* AMDM37x TRM p. 2740 */
    … …  
    128129#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
    129130#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
    130 #define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
    131 #define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
    132 #define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
    133 #define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
     131#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3 << 8)
     132#define AMDM37x_GPT_TCLR_TCM_NO_CAPTURE   (0x0 << 8)
     133#define AMDM37x_GPT_TCLR_TCM_RAISE_CAPTURE   (0x1 << 8)
     134#define AMDM37x_GPT_TCLR_TCM_FALL_CAPTURE   (0x2 << 8)
     135#define AMDM37x_GPT_TCLR_TCM_BOTH_CAPTURE   (0x3 << 8)
     136#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3 << 10)
     137#define AMDM37x_GPT_TCLR_TRG_NO  (0x0 << 10)
     138#define AMDM37x_GPT_TCLR_TRG_OVERFLOW  (0x1 << 10)
     139#define AMDM37x_GPT_TCLR_TRG_OVERMATCH  (0x2 << 10)
    134140#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
    135141#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
    … …  
    209215        timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
    210216
     217        /* Reset the timer */
     218        timer->regs->tiocp_cfg |= AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG;
     219
     220        while (timer->regs->tistat & AMDM37x_GPT_TISTAT_RESET_DONE_FLAG);
     221
    211222        /* Set autoreload */
    212         timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
     223        timer->regs->tclr |= AMDM37x_GPT_TCLR_AR_FLAG;
    213224
    214225        timer->special_available = (
    … …  
    216227            (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
    217228            (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
     229        /* Select reload value */
    218230        timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
     231        /* Set current counter value */
    219232        timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
     233
    220234        if (timer->special_available) {
    221                 /* Set values for according to formula (manual p. 2733) */
     235                /* Set values according to formula (manual p. 2733) */
    222236                /* Use temporary variables for easier debugging */
    223237                const uint32_t tpir =
    224238                    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
    225239                const uint32_t tnir =
    226                     ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
     240                    ((32768 / hz) * 1000000) - (32768000L * (1000 / hz));
    227241                timer->regs->tpir = tpir;
    228242                timer->regs->tnir = tnir;
    … …  
    241255}
    242256
    243 static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
     257static inline bool amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
    244258{
    245259        ASSERT(timer);
    246260        ASSERT(timer->regs);
    247261        /* Clear all pending interrupts */
    248         timer->regs->tisr = timer->regs->tisr;
     262        const uint32_t tisr = timer->regs->tisr;
     263        timer->regs->tisr = tisr;
     264        return tisr != 0;
    249265}
    250266
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