Index: uspace/drv/infrastructure/rootamdm37x/clock_control_cm.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/clock_control_cm.h	(revision 639d9dd5dbb589c4026fb84a13514a88ab38caec)
+++ uspace/drv/infrastructure/rootamdm37x/clock_control_cm.h	(revision f4c9e42b5a946132ad774ff34c173a933febc2b0)
@@ -55,13 +55,11 @@
 #define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG   (1 << 27)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG   (1 << 19)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_SHIFT   (16)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP   (0x1)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK   (0x7)
+#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK   (0x7 << 16)
+#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP   (0x1 << 16)
+#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK   (0x7 << 16)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG   (1 << 12)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG   (1 << 10)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG   (1 << 3)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_SHIFT   (0)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS   (0x5)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK   (0x6)
@@ -72,5 +70,4 @@
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG   (1 << 3)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_SHIFT   (0)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LP_STOP   (0x1)
 #define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LOCK   (0x7)
@@ -100,10 +97,8 @@
 
 	ioport32_t autoidle_pll;
-#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_SHIFT   (3)
-#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED   (0x0)
-#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC   (0x1)
+#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK   (0x7 << 3)
+#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED   (0x0 << 3)
+#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC   (0x1 << 3)
 #define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_SHIFT   (0)
 #define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED   (0x0)
 #define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC   (0x5)
@@ -111,5 +106,4 @@
 	ioport32_t autoidle2_pll;
 #define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_SHIFT   (0)
 #define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED   (0x0)
 #define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC   (0x1)
@@ -118,10 +112,10 @@
 
 	ioport32_t clksel1_pll;
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK   (0x1f)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_SHIFT   (27)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK   (0x7ff)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_SHIFT   (16)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK   (0x7f)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_SHIFT   (8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK   (0x1f << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK   (0x7ff << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK   (0x7f << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV(x)   (((x) & 0x7f) << 8)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG   (1 << 6)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG   (1 << 5)
@@ -129,28 +123,27 @@
 
 	ioport32_t clksel2_pll;
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK   (0xff)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_SHIFT   (24)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_SHIFT   (21)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500   (0x2)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000   (0x4)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK   (0xfff)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_SHIFT   (8)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK   (0xff << 24)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x)   (((x) & 0xff) << 24)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK   (0x7 << 21)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500   (0x2 << 21)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000   (0x4 << 21)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK   (0xfff << 8)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x)   (((x) & 0xfff) << 8)
 #define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK   (0x7f)
-#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_SHIFT   (0)
+#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x)   ((x) & 0x7f)
 
 	ioport32_t clksel3_pll;
 #define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK   (0xf)
-#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_SHIFT   (0)
+#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x)   ((x) & 0xf)
 
 	ioport32_t clksel4_pll;
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK   (0x7ff)
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_SHIFT   (8)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK   (0x7ff << 8)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT(x)   (((x) & 0x7ff) << 8)
 #define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK   (0x7f)
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_SHIFT   (0)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV(x)   ((x) & 0x7f)
 
 	ioport32_t clksel5_pll;
 #define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK   (0x1f)
-#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_SHIFT   (0)
+#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M(x)   ((x) & 0x1f)
 } clock_control_cm_regs_t;
 
