Changeset f6062f15 in mainline
- Timestamp:
- 2011-11-11T17:45:07Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 751d17a2
- Parents:
- 4440581
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/audio/sb16/dma_controller.c
r4440581 rf6062f15 85 85 86 86 uint8_t flip_flop; 87 /* Master reset sets Flip-Flop low, clears status, 88 * sets all mask bits on */ 87 89 uint8_t master_reset; /* Intermediate is not implemented on PCs */ 88 90 uint8_t mask_reset; 89 /* Master reset sets Flip-Flop low, clears status,sets all mask bits on */90 91 91 92 uint8_t multi_mask; … … 123 124 uint8_t flip_flop; 124 125 uint8_t reservedc; 125 uint8_t master_reset _intermediate;126 uint8_t master_reset; 126 127 uint8_t reservedd; 127 128 uint8_t multi_mask; … … 214 215 return EIO; 215 216 controller->initialized = true; 217 218 pio_write_8(&controller->second->master_reset, 0xff); 219 pio_write_8(&controller->first->master_reset, 0xff); 220 221 216 222 return EOK; 217 223 } … … 232 238 233 239 /* 16 bit transfers are a bit special */ 234 ddf_log_debug("Unspoiled address and size: %p(%zu).\n", pa, size);240 ddf_log_debug("Unspoiled address: %p and size: %zu.\n", pa, size); 235 241 if (channel > 4) { 236 242 /* Size is the count of 16bit words */ … … 253 259 /* Set mode */ 254 260 value = DMA_MODE_CHAN_TO_REG(channel) | mode; 261 ddf_log_verbose("Writing mode byte: %p:%hhx.\n", 262 dma_channel.mode_address, value); 255 263 pio_write_8(dma_channel.mode_address, value); 256 264 … … 260 268 /* Low byte */ 261 269 value = pa & 0xff; 262 ddf_log_verbose("Writing address low byte: %hhx.\n", value); 270 ddf_log_verbose("Writing address low byte: %p:%hhx.\n", 271 dma_channel.offset_reg_address, value); 263 272 pio_write_8(dma_channel.offset_reg_address, value); 264 273 265 274 /* High byte */ 266 275 value = (pa >> 8) & 0xff; 267 ddf_log_verbose("Writing address high byte: %hhx.\n", value); 276 ddf_log_verbose("Writing address high byte: %p:%hhx.\n", 277 dma_channel.offset_reg_address, value); 268 278 pio_write_8(dma_channel.offset_reg_address, value); 269 279 270 280 /* Page address - third byte */ 271 281 value = (pa >> 16) & 0xff; 272 ddf_log_verbose("Writing address page byte: %hhx.\n", value); 273 pio_write_8(dma_channel.offset_reg_address, value); 282 ddf_log_verbose("Writing address page byte: %p:%hhx.\n", 283 dma_channel.page_reg_address, value); 284 pio_write_8(dma_channel.page_reg_address, value); 274 285 275 286 /* Set size -- reset flip-flop */ … … 278 289 /* Low byte */ 279 290 value = (size - 1) & 0xff; 280 ddf_log_verbose("Writing size low byte: %hhx.\n", value); 281 pio_write_8(dma_channel.offset_reg_address, value); 291 ddf_log_verbose("Writing size low byte: %p:%hhx.\n", 292 dma_channel.size_reg_address, value); 293 pio_write_8(dma_channel.size_reg_address, value); 282 294 283 295 /* High byte */ 284 296 value = ((size - 1) >> 8) & 0xff; 285 ddf_log_verbose("Writing size high byte: %hhx.\n", value); 286 pio_write_8(dma_channel.offset_reg_address, value); 297 ddf_log_verbose("Writing size high byte: %p:%hhx.\n", 298 dma_channel.size_reg_address, value); 299 pio_write_8(dma_channel.size_reg_address, value); 287 300 288 301 /* Unmask DMA request */
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