Changeset f7bb6d1 in mainline for boot/arch/arm32/src/asm.S

Timestamp:

2013-09-17T19:51:20Z (11 years ago)

Author:

Jakub Klama <jakub.klama@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ac3d27

Parents:

3efc35a (diff), ca62f86 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge from launchpad branch.

File:

• boot/arch/arm32/src/asm.S (modified) (3 diffs)

boot/arch/arm32/src/asm.S

@@ -56 +56 @@
 jump_to_kernel:
         #
-        # TODO
         # Make sure that the I-cache, D-cache and memory are mutually coherent
         # before passing control to the copied code.
@@ -68 +67 @@
 #define CP15_C1_BP              11
 #define CP15_C1_DC              2
-        # Disable I-cache and D-cache before the kernel is started.
+
+
+#ifndef PROCESSOR_ARCH_armv7_a
         mrc     p15, 0, r4, c1, c0, 0
+        
+        # D-cache before the kernel is started.
         bic     r4, r4, #(1 << CP15_C1_DC)
+
+        # Disable I-cache and Branche predictors.
         bic     r4, r4, #(1 << CP15_C1_IC)
         bic     r4, r4, #(1 << CP15_C1_BP)
+        
         mcr     p15, 0, r4, c1, c0, 0
+#endif
+
 
         
@@ -81 +89 @@
 #else
         #cp15 dsb, r4 is ignored (should be zero)
+        mov r4, #0
         mcr p15, 0, r4, c7, c10, 4
 #endif
         
         # Clean ICache and BPredictors, r4 ignored (SBZ)
+        mov r4, #0
         mcr p15, 0, r4, c7, c5, 0
         nop