Changeset f7bb6d1 in mainline for kernel/arch/arm32/src/mm/tlb.c

Timestamp:

2013-09-17T19:51:20Z (11 years ago)

Author:

Jakub Klama <jakub.klama@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ac3d27

Parents:

3efc35a (diff), ca62f86 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge from launchpad branch.

File:

• kernel/arch/arm32/src/mm/tlb.c (modified) (5 diffs)

kernel/arch/arm32/src/mm/tlb.c

@@ -37 +37 @@
 #include <arch/mm/asid.h>
 #include <arch/asm.h>
+#include <arch/cp15.h>
 #include <typedefs.h>
 #include <arch/mm/page.h>
+#include <arch/cache.h>
 
 /** Invalidate all entries in TLB.
@@ -46 +48 @@
 void tlb_invalidate_all(void)
 {
-        asm volatile (
-                "eor r1, r1\n"
-                "mcr p15, 0, r1, c8, c7, 0\n"
-                ::: "r1"
-        );
+        TLBIALL_write(0);
+        /*
+         * "A TLB maintenance operation is only guaranteed to be complete after
+         * the execution of a DSB instruction."
+         * "An ISB instruction, or a return from an exception, causes the
+         * effect of all completed TLB maintenance operations that appear in
+         * program order before the ISB or return from exception to be visible
+         * to all subsequent instructions, including the instruction fetches
+         * for those instructions."
+         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
+         */
+        read_barrier();
+        inst_barrier();
 }
 
@@ -60 +70 @@
 {
         tlb_invalidate_all();
+        // TODO: why not TLBIASID_write(asid) ?
 }
 
@@ -65 +76 @@
  *
  * @param page Virtual adress of the page
- */ 
+ */
 static inline void invalidate_page(uintptr_t page)
 {
-        asm volatile (
-                "mcr p15, 0, %[page], c8, c7, 1\n"
-                :: [page] "r" (page)
-        );
+        //TODO: What about TLBIMVAA?
+        TLBIMVA_write(page);
+        /*
+         * "A TLB maintenance operation is only guaranteed to be complete after
+         * the execution of a DSB instruction."
+         * "An ISB instruction, or a return from an exception, causes the
+         * effect of all completed TLB maintenance operations that appear in
+         * program order before the ISB or return from exception to be visible
+         * to all subsequent instructions, including the instruction fetches
+         * for those instructions."
+         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
+         */
+        read_barrier();
+        inst_barrier();
 }
 
@@ -83 +104 @@
 void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
 {
-        unsigned int i;
-
-        for (i = 0; i < cnt; i++)
+        for (unsigned i = 0; i < cnt; i++)
                 invalidate_page(page + i * PAGE_SIZE);
 }