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  • kernel/arch/arm32/src/mm/tlb.c

    r9d58539 rf834cc32  
    3737#include <arch/mm/asid.h>
    3838#include <arch/asm.h>
     39#include <arch/cp15.h>
    3940#include <typedefs.h>
    4041#include <arch/mm/page.h>
     42#include <arch/cache.h>
    4143
    4244/** Invalidate all entries in TLB.
     
    4648void tlb_invalidate_all(void)
    4749{
    48         asm volatile (
    49                 "eor r1, r1\n"
    50                 "mcr p15, 0, r1, c8, c7, 0\n"
    51                 ::: "r1"
    52         );
     50        TLBIALL_write(0);
     51        /*
     52         * "A TLB maintenance operation is only guaranteed to be complete after
     53         * the execution of a DSB instruction."
     54         * "An ISB instruction, or a return from an exception, causes the
     55         * effect of all completed TLB maintenance operations that appear in
     56         * program order before the ISB or return from exception to be visible
     57         * to all subsequent instructions, including the instruction fetches
     58         * for those instructions."
     59         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
     60         */
     61        read_barrier();
     62        inst_barrier();
    5363}
    5464
     
    6070{
    6171        tlb_invalidate_all();
     72        // TODO: why not TLBIASID_write(asid) ?
    6273}
    6374
     
    6576 *
    6677 * @param page Virtual adress of the page
    67  */ 
     78 */
    6879static inline void invalidate_page(uintptr_t page)
    6980{
    70         asm volatile (
    71                 "mcr p15, 0, %[page], c8, c7, 1\n"
    72                 :: [page] "r" (page)
    73         );
     81#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
     82        if (TLBTR_read() & TLBTR_SEP_FLAG) {
     83                ITLBIMVA_write(page);
     84                DTLBIMVA_write(page);
     85        } else {
     86                TLBIMVA_write(page);
     87        }
     88#elif defined(PROCESSOR_arm920t)
     89        ITLBIMVA_write(page);
     90        DTLBIMVA_write(page);
     91#elif defined(PROCESSOR_arm926ej_s)
     92        TLBIMVA_write(page);
     93#else
     94#error Unknown TLB type
     95#endif
     96
     97        /*
     98         * "A TLB maintenance operation is only guaranteed to be complete after
     99         * the execution of a DSB instruction."
     100         * "An ISB instruction, or a return from an exception, causes the
     101         * effect of all completed TLB maintenance operations that appear in
     102         * program order before the ISB or return from exception to be visible
     103         * to all subsequent instructions, including the instruction fetches
     104         * for those instructions."
     105         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
     106         */
     107        read_barrier();
     108        inst_barrier();
    74109}
    75110
     
    83118void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
    84119{
    85         unsigned int i;
    86 
    87         for (i = 0; i < cnt; i++)
     120        for (unsigned i = 0; i < cnt; i++)
    88121                invalidate_page(page + i * PAGE_SIZE);
    89122}
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