Changes in / [1ce4189:f8e549b] in mainline
- Files:
-
- 11 edited
-
kernel/generic/include/ddi/irq.h (modified) (2 diffs)
-
kernel/generic/src/ipc/irq.c (modified) (4 diffs)
-
uspace/drv/ehci-hcd/ehci-hcd.ma (modified) (1 diff)
-
uspace/drv/ehci-hcd/pci.c (modified) (1 diff)
-
uspace/drv/ohci/hc.c (modified) (6 diffs)
-
uspace/drv/ohci/hc.h (modified) (2 diffs)
-
uspace/drv/ohci/ohci.c (modified) (1 diff)
-
uspace/drv/ohci/ohci.ma (modified) (1 diff)
-
uspace/drv/ohci/ohci_regs.h (modified) (1 diff)
-
uspace/drv/ohci/pci.c (modified) (2 diffs)
-
uspace/lib/usb/src/host/batch.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/generic/include/ddi/irq.h
r1ce4189 rf8e549b 77 77 */ 78 78 CMD_PIO_WRITE_A_32, 79 80 /** Read 1 byte from the memory space. */ 81 CMD_MEM_READ_8, 82 /** Read 2 bytes from the memory space. */ 83 CMD_MEM_READ_16, 84 /** Read 4 bytes from the memory space. */ 85 CMD_MEM_READ_32, 86 87 /** Write 1 byte to the memory space. */ 88 CMD_MEM_WRITE_8, 89 /** Write 2 bytes to the memory space. */ 90 CMD_MEM_WRITE_16, 91 /** Write 4 bytes to the memory space. */ 92 CMD_MEM_WRITE_32, 93 94 /** Write 1 byte from the source argument to the memory space. */ 95 CMD_MEM_WRITE_A_8, 96 /** Write 2 bytes from the source argument to the memory space. */ 97 CMD_MEM_WRITE_A_16, 98 /** Write 4 bytes from the source argument to the memory space. */ 99 CMD_MEM_WRITE_A_32, 100 79 101 80 /** 102 81 * Perform a bit masking on the source argument … … 224 203 /** Notification configuration structure. */ 225 204 ipc_notif_cfg_t notif_cfg; 226 227 as_t *driver_as;228 205 } irq_t; 229 206 -
kernel/generic/src/ipc/irq.c
r1ce4189 rf8e549b 174 174 irq->notif_cfg.code = code; 175 175 irq->notif_cfg.counter = 0; 176 irq->driver_as = AS;177 176 178 177 /* … … 365 364 return IRQ_DECLINE; 366 365 367 #define CMD_MEM_READ(target) \368 do { \369 void *va = code->cmds[i].addr; \370 if (AS != irq->driver_as) \371 as_switch(AS, irq->driver_as); \372 printf("Copying data from address: %p.\n", va); \373 memcpy_from_uspace(&target, va, (sizeof(target))); \374 if (dstarg) \375 scratch[dstarg] = target; \376 } while(0)377 378 #define CMD_MEM_WRITE(val) \379 do { \380 void *va = code->cmds[i].addr; \381 if (AS != irq->driver_as) \382 as_switch(AS, irq->driver_as); \383 printf("Writing data to address: %p.\n", va); \384 memcpy_to_uspace(va, &val, sizeof(val)); \385 } while (0)386 387 as_t *current_as = AS;388 366 size_t i; 389 367 for (i = 0; i < code->cmdcount; i++) { … … 444 422 } 445 423 break; 446 case CMD_MEM_READ_8: {447 uint8_t val;448 CMD_MEM_READ(val);449 break;450 }451 case CMD_MEM_READ_16: {452 uint16_t val;453 CMD_MEM_READ(val);454 break;455 }456 case CMD_MEM_READ_32: {457 uint32_t val;458 CMD_MEM_READ(val);459 printf("mem READ value: %x.\n", val);460 break;461 }462 case CMD_MEM_WRITE_8: {463 uint8_t val = code->cmds[i].value;464 CMD_MEM_WRITE(val);465 break;466 }467 case CMD_MEM_WRITE_16: {468 uint16_t val = code->cmds[i].value;469 CMD_MEM_WRITE(val);470 break;471 }472 case CMD_MEM_WRITE_32: {473 uint32_t val = code->cmds[i].value;474 CMD_MEM_WRITE(val);475 break;476 }477 case CMD_MEM_WRITE_A_8:478 if (srcarg) {479 uint8_t val = scratch[srcarg];480 CMD_MEM_WRITE(val);481 }482 break;483 case CMD_MEM_WRITE_A_16:484 if (srcarg) {485 uint16_t val = scratch[srcarg];486 CMD_MEM_WRITE(val);487 }488 break;489 case CMD_MEM_WRITE_A_32:490 if (srcarg) {491 uint32_t val = scratch[srcarg];492 CMD_MEM_WRITE(val);493 }494 break;495 424 case CMD_BTEST: 496 425 if ((srcarg) && (dstarg)) { … … 506 435 break; 507 436 case CMD_ACCEPT: 508 if (AS != current_as)509 as_switch(AS, current_as);510 437 return IRQ_ACCEPT; 511 438 case CMD_DECLINE: 512 439 default: 513 if (AS != current_as)514 as_switch(AS, current_as);515 440 return IRQ_DECLINE; 516 441 } 517 442 } 518 if (AS != current_as)519 as_switch(AS, current_as);520 443 521 444 return IRQ_DECLINE; -
uspace/drv/ehci-hcd/ehci-hcd.ma
r1ce4189 rf8e549b 2 2 10 pci/ven=1002&dev=4386 3 3 10 pci/ven=1002&dev=4396 4 10 pci/ven=1002&dev=43735 4 10 pci/ven=1022&dev=7463 6 5 10 pci/ven=1022&dev=7808 -
uspace/drv/ehci-hcd/pci.c
r1ce4189 rf8e549b 186 186 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read PCI config space.\n", 187 187 ret); 188 usb_log_info("Register space BAR at %p:%" PRIxn ".\n", 189 (void *) address, value); 188 usb_log_info("Register space BAR at %p:%" PRIxn ".\n", (void *) address, value); 190 189 191 190 /* clear lower byte, it's not part of the BASE address */ -
uspace/drv/ohci/hc.c
r1ce4189 rf8e549b 45 45 #include "hcd_endpoint.h" 46 46 47 #define OHCI_USED_INTERRUPTS \48 (I_SO | I_WDH | I_UE | I_RHSC)49 47 static int interrupt_emulator(hc_t *instance); 50 48 static void hc_gain_control(hc_t *instance); … … 287 285 { 288 286 assert(instance); 287 if ((status & ~IS_SF) == 0) /* ignore sof status */ 288 return; 289 if (status & IS_RHSC) 290 rh_interrupt(&instance->rh); 291 289 292 usb_log_debug("OHCI interrupt: %x.\n", status); 290 if ((status & ~I_SF) == 0) /* ignore sof status */ 291 return; 292 if (status & I_RHSC) 293 rh_interrupt(&instance->rh); 294 295 296 if (status & I_WDH) { 293 294 if (status & IS_WDH) { 297 295 fibril_mutex_lock(&instance->guard); 298 296 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca, … … 334 332 { 335 333 assert(instance); 336 usb_log_debug("Requesting OHCI control.\n");337 334 /* Turn off legacy emulation */ 338 335 volatile uint32_t *ohci_emulation_reg = … … 340 337 usb_log_debug("OHCI legacy register %p: %x.\n", 341 338 ohci_emulation_reg, *ohci_emulation_reg); 342 *ohci_emulation_reg &= ~0x1;339 *ohci_emulation_reg = 0; 343 340 344 341 /* Interrupt routing enabled => smm driver is active */ … … 424 421 instance->registers->control); 425 422 426 /* Enable interrupts */ 427 instance->registers->interrupt_enable = OHCI_USED_INTERRUPTS; 423 /* Disable interrupts */ 424 instance->registers->interrupt_disable = I_SF | I_OC; 425 usb_log_debug2("Disabling interrupts: %x.\n", 426 instance->registers->interrupt_disable); 427 instance->registers->interrupt_disable = I_MI; 428 428 usb_log_debug2("Enabled interrupts: %x.\n", 429 429 instance->registers->interrupt_enable); 430 instance->registers->interrupt_enable = I_MI;431 430 432 431 /* Set periodic start to 90% */ … … 493 492 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa); 494 493 495 /* Init interrupt code */496 instance->interrupt_code.cmds = instance->interrupt_commands;497 {498 /* Read status register */499 instance->interrupt_commands[0].cmd = CMD_MEM_READ_32;500 instance->interrupt_commands[0].dstarg = 1;501 instance->interrupt_commands[0].addr =502 (void*)&instance->registers->interrupt_status;503 504 /* Test whether we are the interrupt cause */505 instance->interrupt_commands[1].cmd = CMD_BTEST;506 instance->interrupt_commands[1].value =507 OHCI_USED_INTERRUPTS;508 instance->interrupt_commands[1].srcarg = 1;509 instance->interrupt_commands[1].dstarg = 2;510 511 /* Predicate cleaning and accepting */512 instance->interrupt_commands[2].cmd = CMD_PREDICATE;513 instance->interrupt_commands[2].value = 2;514 instance->interrupt_commands[2].srcarg = 2;515 516 /* Write clean status register */517 instance->interrupt_commands[3].cmd = CMD_MEM_WRITE_A_32;518 instance->interrupt_commands[3].srcarg = 1;519 instance->interrupt_commands[3].addr =520 (void*)&instance->registers->interrupt_status;521 522 /* Accept interrupt */523 instance->interrupt_commands[4].cmd = CMD_ACCEPT;524 525 instance->interrupt_code.cmdcount = OHCI_NEEDED_IRQ_COMMANDS;526 }527 528 494 return EOK; 529 495 } -
uspace/drv/ohci/hc.h
r1ce4189 rf8e549b 51 51 #include "hw_struct/hcca.h" 52 52 53 #define OHCI_NEEDED_IRQ_COMMANDS 554 55 53 typedef struct hc { 56 54 ohci_regs_t *registers; … … 67 65 fid_t interrupt_emulator; 68 66 fibril_mutex_t guard; 69 70 /** Code to be executed in kernel interrupt handler */71 irq_code_t interrupt_code;72 73 /** Commands that form interrupt code */74 irq_cmd_t interrupt_commands[OHCI_NEEDED_IRQ_COMMANDS];75 67 } hc_t; 76 68 -
uspace/drv/ohci/ohci.c
r1ce4189 rf8e549b 202 202 203 203 /* It does no harm if we register this on polling */ 204 ret = register_interrupt_handler(device, irq, irq_handler, 205 &instance->hc.interrupt_code); 204 ret = register_interrupt_handler(device, irq, irq_handler, NULL); 206 205 CHECK_RET_FINI_RETURN(ret, 207 206 "Failed(%d) to register interrupt handler.\n", ret); -
uspace/drv/ohci/ohci.ma
r1ce4189 rf8e549b 1 1 10 pci/ven=106b&dev=003f 2 2 10 pci/ven=10de&dev=0aa5 3 4 10 pci/ven=1002&dev=4374 5 10 pci/ven=1002&dev=4375 6 7 10 pci/ven=1002&dev=4387 8 10 pci/ven=1002&dev=4388 9 10 pci/ven=1002&dev=4389 10 10 pci/ven=1002&dev=438a 11 10 pci/ven=1002&dev=438b 3 10 pci/ven=10de&dev=0aa5 -
uspace/drv/ohci/ohci_regs.h
r1ce4189 rf8e549b 72 72 #define CS_SOC_SHIFT (16) 73 73 74 /** Interupt enable/disable/status,75 * reads give the same value,76 * writing causes enable/disable,77 * status is write-clean (writing 1 clears the bit*/78 74 volatile uint32_t interrupt_status; 75 #define IS_SO (1 << 0) /* Scheduling overrun */ 76 #define IS_WDH (1 << 1) /* Write-back done head */ 77 #define IS_SF (1 << 2) /* Start of frame */ 78 #define IS_RD (1 << 3) /* Resume detected */ 79 #define IS_UE (1 << 4) /* Unrecoverable error */ 80 #define IS_FNO (1 << 5) /* Frame number overflow */ 81 #define IS_RHSC (1 << 6) /* Root hub status change */ 82 #define IS_OC (1 << 30) /* Ownership change */ 83 84 /** Interupt enable/disable, reads give the same value, writing causes 85 * enable/disable */ 79 86 volatile uint32_t interrupt_enable; 80 87 volatile uint32_t interrupt_disable; -
uspace/drv/ohci/pci.c
r1ce4189 rf8e549b 46 46 47 47 #include "pci.h" 48 49 #define PAGE_SIZE_MASK 0xfffff000 50 51 #define HCC_PARAMS_OFFSET 0x8 52 #define HCC_PARAMS_EECP_MASK 0xff 53 #define HCC_PARAMS_EECP_OFFSET 8 54 55 #define CMD_OFFSET 0x0 56 #define CONFIGFLAG_OFFSET 0x40 57 58 #define USBCMD_RUN 1 59 60 #define USBLEGSUP_OFFSET 0 61 #define USBLEGSUP_BIOS_CONTROL (1 << 16) 62 #define USBLEGSUP_OS_CONTROL (1 << 24) 63 #define USBLEGCTLSTS_OFFSET 4 64 65 #define DEFAULT_WAIT 10000 66 #define WAIT_STEP 10 48 67 49 68 /** Get address of registers and IRQ for given device. … … 127 146 int pci_enable_interrupts(ddf_dev_t *device) 128 147 { 148 return ENOTSUP; 129 149 int parent_phone = 130 150 devman_parent_device_connect(device->handle, IPC_FLAG_BLOCKING); -
uspace/lib/usb/src/host/batch.c
r1ce4189 rf8e549b 128 128 memcpy(instance->buffer, instance->data_buffer, instance->buffer_size); 129 129 130 usb_log_debug("Batch (%p)done (T%d.%d, %s %s in, %zuB): %s (%d).\n",130 usb_log_debug("Batch %p done (T%d.%d, %s %s in, %zuB): %s (%d).\n", 131 131 instance, instance->ep->address, instance->ep->endpoint, 132 132 usb_str_speed(instance->ep->speed), 133 133 usb_str_transfer_type_short(instance->ep->transfer_type), 134 instance->transfered_size, str_error(instance->error), 135 instance->error); 134 instance->transfered_size, str_error(instance->error), instance->error); 136 135 137 136 instance->callback_in(instance->fun, instance->error, … … 148 147 assert(instance->callback_out); 149 148 150 usb_log_debug("Batch (%p)done (T%d.%d, %s %s out): %s (%d).\n",149 usb_log_debug("Batch %p done (T%d.%d, %s %s out): %s (%d).\n", 151 150 instance, instance->ep->address, instance->ep->endpoint, 152 151 usb_str_speed(instance->ep->speed),
Note:
See TracChangeset
for help on using the changeset viewer.
