Changeset f92f6b1 in mainline
- Timestamp:
- 2018-01-10T01:11:01Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4a00bc9
- Parents:
- 708d8fcd
- Location:
- uspace/drv/bus/usb/xhci
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/endpoint.c
r708d8fcd rf92f6b1 314 314 } 315 315 316 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) { 317 for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) { 318 dma_buffer_free(&xhci_ep->isoch->transfers[i].data); 319 } 320 } 316 isoch_fini(xhci_ep); 321 317 } 322 318 -
uspace/drv/bus/usb/xhci/isoch.c
r708d8fcd rf92f6b1 35 35 36 36 #include <str_error.h> 37 #include <macros.h> 37 38 38 39 #include "endpoint.h" … … 56 57 ? desc->companion.bytes_per_interval 57 58 : ep->base.max_transfer_size; 58 /* Technically there could be superspeed plus too. */ 59 60 const xhci_hc_t *hc = bus_to_xhci_bus(ep->base.device->bus)->hc; 61 62 /* 63 * We shall cover at least twice the IST period, otherwise we will get 64 * an over/underrun every time. 65 */ 66 isoch->buffer_count = (2 * hc->ist) / ep->interval; 67 68 /* 2 buffers are the very minimum. */ 69 isoch->buffer_count = max(2, isoch->buffer_count); 70 71 usb_log_error("[isoch] isoch setup with %zu buffers", isoch->buffer_count); 59 72 } 60 73 … … 66 79 isoch->dequeue = isoch->enqueue = isoch->hw_enqueue = 0; 67 80 68 for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) {81 for (size_t i = 0; i < isoch->buffer_count; ++i) { 69 82 isoch->transfers[i].state = ISOCH_EMPTY; 70 83 } … … 85 98 } 86 99 87 for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) 88 dma_buffer_free(&isoch->transfers[i].data); 100 if (isoch->transfers) { 101 for (size_t i = 0; i < isoch->buffer_count; ++i) 102 dma_buffer_free(&isoch->transfers[i].data); 103 free(isoch->transfers); 104 } 89 105 } 90 106 … … 100 116 return ENOMEM; 101 117 102 for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) { 118 isoch->transfers = calloc(isoch->buffer_count, sizeof(xhci_isoch_transfer_t)); 119 if(!isoch->transfers) 120 goto err; 121 122 for (size_t i = 0; i < isoch->buffer_count; ++i) { 103 123 xhci_isoch_transfer_t *transfer = &isoch->transfers[i]; 104 124 if (dma_buffer_alloc(&transfer->data, isoch->max_size)) { 105 isoch_fini(ep); 106 return ENOMEM; 125 goto err; 107 126 } 108 127 } … … 113 132 114 133 return EOK; 134 err: 135 isoch_fini(ep); 136 return ENOMEM; 115 137 } 116 138 … … 151 173 * buffers */ 152 174 it->mfindex = XHCI_REG_RD(hc->rt_regs, XHCI_RT_MFINDEX) + 1 153 + XHCI_ISOCH_BUFFER_COUNT* ep->interval175 + isoch->buffer_count * ep->interval 154 176 + hc->ist; 155 177 … … 207 229 * TODO: The "size" of the clock is too low. We have to scale it a bit 208 230 * to ensure correct scheduling of transfers, that are 209 * XHCI_ISOCH_BUFFER_COUNT* interval away from now.231 * buffer_count * interval away from now. 210 232 * Maximum interval is 8 seconds, which means we need a size of 211 233 * 16 seconds. The size of MFIINDEX is 2 seconds only. … … 268 290 } 269 291 270 isoch->hw_enqueue = (isoch->hw_enqueue + 1) % XHCI_ISOCH_BUFFER_COUNT;292 isoch->hw_enqueue = (isoch->hw_enqueue + 1) % isoch->buffer_count; 271 293 break; 272 294 … … 279 301 it->size = 0; 280 302 281 isoch->hw_enqueue = (isoch->hw_enqueue + 1) % XHCI_ISOCH_BUFFER_COUNT;303 isoch->hw_enqueue = (isoch->hw_enqueue + 1) % isoch->buffer_count; 282 304 break; 283 305 } … … 353 375 /* fallthrough */ 354 376 case WINDOW_INSIDE: 355 isoch->enqueue = (isoch->enqueue + 1) % XHCI_ISOCH_BUFFER_COUNT;377 isoch->enqueue = (isoch->enqueue + 1) % isoch->buffer_count; 356 378 isoch->last_mfindex = it->mfindex; 357 379 … … 417 439 } 418 440 419 isoch->enqueue = (isoch->enqueue + 1) % XHCI_ISOCH_BUFFER_COUNT;441 isoch->enqueue = (isoch->enqueue + 1) % isoch->buffer_count; 420 442 421 443 /* Withdraw results from previous transfers. */ … … 423 445 xhci_isoch_transfer_t *res = &isoch->transfers[isoch->dequeue]; 424 446 while (res->state == ISOCH_COMPLETE) { 425 isoch->dequeue = (isoch->dequeue + 1) % XHCI_ISOCH_BUFFER_COUNT;447 isoch->dequeue = (isoch->dequeue + 1) % isoch->buffer_count; 426 448 427 449 res->state = ISOCH_EMPTY; … … 487 509 } 488 510 489 isoch->dequeue = (isoch->dequeue + 1) % XHCI_ISOCH_BUFFER_COUNT;511 isoch->dequeue = (isoch->dequeue + 1) % isoch->buffer_count; 490 512 491 513 /* Withdraw results from previous transfer. */ … … 543 565 * which one it is. 544 566 */ 545 for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) {567 for (size_t i = 0; i < isoch->buffer_count; ++i) { 546 568 xhci_isoch_transfer_t * const it = &isoch->transfers[i]; 547 569 -
uspace/drv/bus/usb/xhci/isoch.h
r708d8fcd rf92f6b1 87 87 uint32_t last_mfindex; 88 88 89 /** The number of transfer buffers allocated */ 90 size_t buffer_count; 91 89 92 /** Isochronous scheduled transfers with respective buffers */ 90 #define XHCI_ISOCH_BUFFER_COUNT 4 91 xhci_isoch_transfer_t transfers[XHCI_ISOCH_BUFFER_COUNT]; 93 xhci_isoch_transfer_t *transfers; 92 94 93 95 /** -
uspace/drv/bus/usb/xhci/main.c
r708d8fcd rf92f6b1 115 115 { 116 116 log_init(NAME); 117 logctl_set_log_level(NAME, LVL_ DEBUG2);117 logctl_set_log_level(NAME, LVL_NOTE); 118 118 return hc_driver_main(&xhci_driver); 119 119 }
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