Changeset f9a56c0 in mainline


Ignore:
Timestamp:
2006-08-17T11:39:38Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
ee289cf0
Parents:
ec2c55a
Message:

sparc64 work.
interrupt_vector trap experimental handling.
Minimal reverse-engineered FireHose Controller driver (documentation needed!).
Keyboard on Sun Enterprise is now interrupt driven. Keyboard on Sun Ultra
is still polled.

Location:
kernel
Files:
2 added
13 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/Makefile.inc

    rec2c55a rf9a56c0  
    6767
    6868        CONFIG_Z8530 = y
    69         DEFS += -DCONFIG_Z8530
     69        DEFS += -DCONFIG_Z8530 
    7070endif
    7171ifeq ($(MACHINE),ultra)
    … …  
    102102        arch/$(ARCH)/src/drivers/tick.c \
    103103        arch/$(ARCH)/src/drivers/kbd.c
     104
     105ifdef CONFIG_Z8530
     106ARCH_SOURCES += \
     107        arch/$(ARCH)/src/drivers/fhc.c
     108endif

  • kernel/arch/sparc64/include/asm.h

    rec2c55a rf9a56c0  
    140140}
    141141
     142/** Write SET_SOFTINT Register.
     143 *
     144 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
     145 *
     146 * @param v New value of SET_SOFTINT register.
     147 */
     148static inline void set_softint_write(uint64_t v)
     149{
     150        __asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
     151}
     152
    142153/** Enable interrupts.
    143154 *

  • kernel/arch/sparc64/include/drivers/ns16550.h

    rec2c55a rf9a56c0  
    4040
    4141#define RBR_REG         0       /** Receiver Buffer Register. */
     42#define IER_REG         1       /** Interrupt Enable Register. */
    4243#define LSR_REG         5       /** Line Status Register. */
    4344
    … …  
    4546{
    4647        return kbd_virt_address[RBR_REG];
     48}
     49
     50static inline uint8_t ns16550_ier_read(void)
     51{
     52        return kbd_virt_address[IER_REG];
     53}
     54
     55static inline void ns16550_ier_write(uint8_t v)
     56{
     57        kbd_virt_address[IER_REG] = v;
    4758}
    4859

  • kernel/arch/sparc64/include/drivers/z8530.h

    rec2c55a rf9a56c0  
    7171#define RR15    15
    7272
     73/* Write Register 0 */
     74#define WR0_ERR_RST     (0x6<<3)
     75
    7376/* Write Register 1 */
    7477#define WR1_RID         (0x0<<3)        /** Receive Interrupts Disabled. */

  • kernel/arch/sparc64/include/mm/mmu.h

    rec2c55a rf9a56c0  
    3636#define __sparc64_MMU_H__
    3737
    38 /** LSU Control Register ASI. */
     38/* LSU Control Register ASI. */
    3939#define ASI_LSU_CONTROL_REG             0x45    /**< Load/Store Unit Control Register. */
    4040
    41 /** I-MMU ASIs. */
     41/* I-MMU ASIs. */
    4242#define ASI_IMMU                        0x50
    4343#define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    … …  
    4848#define ASI_IMMU_DEMAP                  0x57
    4949
    50 /** Virtual Addresses within ASI_IMMU. */
     50/* Virtual Addresses within ASI_IMMU. */
    5151#define VA_IMMU_TAG_TARGET              0x0     /**< IMMU tag target register. */
    5252#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    … …  
    5454#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    5555
    56 /** D-MMU ASIs. */
     56/* D-MMU ASIs. */
    5757#define ASI_DMMU                        0x58
    5858#define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    … …  
    6464#define ASI_DMMU_DEMAP                  0x5f
    6565
    66 /** Virtual Addresses within ASI_DMMU. */
     66/* Virtual Addresses within ASI_DMMU. */
    6767#define VA_DMMU_TAG_TARGET              0x0     /**< DMMU tag target register. */
    6868#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */

  • kernel/arch/sparc64/include/trap/interrupt.h

    rec2c55a rf9a56c0  
    4141#include <arch/stack.h>
    4242
     43/* Interrupt ASI registers. */
     44#define ASI_UDB_INTR_W                  0x77
     45#define ASI_INTR_DISPATCH_STATUS        0x48
     46#define ASI_UDB_INTR_R                  0x7f
     47#define ASI_INTR_RECEIVE                0x49
     48
     49/* VA's used with ASI_UDB_INTR_W register. */
     50#define ASI_UDB_INTR_W_DATA_0   0x40
     51#define ASI_UDB_INTR_W_DATA_1   0x50
     52#define ASI_UDB_INTR_W_DATA_2   0x60
     53
     54/* VA's used with ASI_UDB_INTR_R register. */
     55#define ASI_UDB_INTR_R_DATA_0   0x40
     56#define ASI_UDB_INTR_R_DATA_1   0x50
     57#define ASI_UDB_INTR_R_DATA_2   0x60
     58
    4359#define TT_INTERRUPT_LEVEL_1                    0x41
    4460#define TT_INTERRUPT_LEVEL_2                    0x42
    … …  
    7187
    7288.macro INTERRUPT_VECTOR_TRAP_HANDLER
     89        save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
     90        SIMPLE_HANDLER interrupt
     91        restore
    7392        retry
    7493.endm
    7594#endif /* __ASM__ */
     95
     96#ifndef __ASM__
     97extern void interrupt(void);
     98#endif /* !def __ASM__ */
    7699
    77100#endif

  • kernel/arch/sparc64/src/console.c

    rec2c55a rf9a56c0  
    8585        while (1) {
    8686#ifdef CONFIG_Z8530
    87                 z8530_poll();
     87                return;
    8888#endif
    8989#ifdef CONFIG_NS16550

  • kernel/arch/sparc64/src/drivers/kbd.c

    rec2c55a rf9a56c0  
    6161         * However, the physical keyboard address can
    6262         * be pretty much unaligned on some systems
    63          * (e.g. Ultra 5, Ultras 60).
     63         * (e.g. Ultra 5, Ultra 60).
    6464         */
    6565        aligned_addr = ALIGN_DOWN(bootinfo.keyboard.addr, PAGE_SIZE);

  • kernel/arch/sparc64/src/drivers/tick.c

    rec2c55a rf9a56c0  
    2727 */
    2828
    29  /** @addtogroup sparc64       
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    8989}
    9090
    91  /** @}
     91/** @}
    9292 */
    93 

  • kernel/arch/sparc64/src/trap/interrupt.c

    rec2c55a rf9a56c0  
    3434
    3535#include <arch/interrupt.h>
     36#include <arch/trap/interrupt.h>
    3637#include <interrupt.h>
     38#include <arch/drivers/fhc.h>
    3739#include <arch/types.h>
    3840#include <debug.h>
    3941#include <ipc/sysipc.h>
     42#include <arch/asm.h>
     43#include <arch/barrier.h>
     44
     45#include <genarch/kbd/z8530.h>
    4046
    4147/** Register Interrupt Level Handler.
    … …  
    5965}
    6066
     67void interrupt(void)
     68{
     69        uint64_t intrcv;
     70        uint64_t data0;
     71
     72        intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
     73        data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
     74
     75        switch (data0) {
     76#ifdef CONFIG_Z8530
     77        case Z8530_INTRCV_DATA0:
     78                /*
     79                 * So far, we know we got this interrupt through the FHC.
     80                 * Since we don't have enough information about the FHC and
     81                 * because the interrupt looks like level sensitive,
     82                 * we cannot handle it by scheduling one of the level
     83                 * interrupt traps. Call the interrupt handler directly.
     84                 */
     85                fhc_uart_reset();
     86                z8530_interrupt();
     87                break;
     88#endif
     89        }
     90
     91        membar();
     92        asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
     93}
     94
    6195/** @}
    6296 */
    63 

  • kernel/doc/arch/sparc64

    rec2c55a rf9a56c0  
    77The goal is to provide support for UltraSPARC
    88implementation of SPARC V9 architecture.
     9
     10MACHINES
     11        o Sun Ultra 5
     12        o Sun Enterprise E6500 (simulated)
     13               
     14CPU
     15        o UltraSPARC II
     16        o UltraSPARC IIi
     17
     18SIMULATORS
     19        o simics 2.2.19, simics 3.0.17
     20                                               
     21TOOLCHAIN REQUIREMENTS
     22        o binutils 2.17
     23        o gcc 4.1.1
     24        o older versions may do as well, but are now obsoleted

  • kernel/genarch/include/kbd/z8530.h

    rec2c55a rf9a56c0  
    3838#define KERN_Z8530_H_
    3939
     40#define Z8530_INTRCV_DATA0      0x39    /* hardcoded for use in Simics */
     41
    4042extern void z8530_init(void);
    4143extern void z8530_poll(void);
    4244extern void z8530_grab(void);
    4345extern void z8530_release(void);
     46extern void z8530_interrupt(void);
    4447
    4548#endif

  • kernel/genarch/src/kbd/z8530.c

    rec2c55a rf9a56c0  
    3939#include <genarch/kbd/scanc.h>
    4040#include <genarch/kbd/scanc_sun.h>
     41#include <arch/drivers/fhc.h>
    4142#include <arch/drivers/z8530.h>
    42 #include <arch/drivers/kbd.h>
    4343#include <arch/interrupt.h>
    4444#include <cpu.h>
    … …  
    6565};
    6666
    67 void z8530_interrupt(int n, istate_t *istate);
    6867void z8530_wait(void);
    6968
    … …  
    7271{
    7372}
     73
    7474/** Resume the former interrupt vector */
    7575void z8530_release(void)
    7676{
    7777}
    78 
    79 #include <print.h>
    8078
    8179/** Initialize z8530. */
    … …  
    8583        stdin = &kbrd;
    8684
     85        (void) z8530_read_a(RR8);
     86
    8787        z8530_write_a(WR1, WR1_IARCSC); /* interrupt on all characters */
    88         z8530_write_a(WR2, 12);         /* FIXME: IRQ12 ??? */
    8988
    9089        /* 8 bits per character and enable receiver */
    … …  
    9291       
    9392        z8530_write_a(WR9, WR9_MIE);    /* Master Interrupt Enable. */
     93       
     94        /*
     95         * We need to initialize the FireHose Controller,
     96         * to which is this z8530 attached. Otherwise
     97         * interrupts generated by the z8530 would not
     98         * be forwarded to the CPU.
     99         */
     100        fhc_init();
    94101}
    95102
    … …  
    99106 * @param istate Interrupted state.
    100107 */
    101 void z8530_interrupt(int n, istate_t *istate)
     108void z8530_interrupt(void)
    102109{
     110        z8530_poll();
    103111}
    104112
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