Changeset f9a56c0 in mainline for kernel/arch/sparc64/include/mm/mmu.h

Timestamp:

2006-08-17T11:39:38Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ee289cf0

Parents:

ec2c55a

Message:

sparc64 work.
interrupt_vector trap experimental handling.
Minimal reverse-engineered FireHose Controller driver (documentation needed!).
Keyboard on Sun Enterprise is now interrupt driven. Keyboard on Sun Ultra
is still polled.

File:

• kernel/arch/sparc64/include/mm/mmu.h (modified) (4 diffs)

kernel/arch/sparc64/include/mm/mmu.h

@@ -36 +36 @@
 #define __sparc64_MMU_H__
 
-/** LSU Control Register ASI. */
+/* LSU Control Register ASI. */
 #define ASI_LSU_CONTROL_REG             0x45    /**< Load/Store Unit Control Register. */
 
-/** I-MMU ASIs. */
+/* I-MMU ASIs. */
 #define ASI_IMMU                        0x50
 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51    
@@ -48 +48 @@
 #define ASI_IMMU_DEMAP                  0x57
 
-/** Virtual Addresses within ASI_IMMU. */
+/* Virtual Addresses within ASI_IMMU. */
 #define VA_IMMU_TAG_TARGET              0x0     /**< IMMU tag target register. */
 #define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
@@ -54 +54 @@
 #define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
 
-/** D-MMU ASIs. */
+/* D-MMU ASIs. */
 #define ASI_DMMU                        0x58
 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59    
@@ -64 +64 @@
 #define ASI_DMMU_DEMAP                  0x5f
 
-/** Virtual Addresses within ASI_DMMU. */
+/* Virtual Addresses within ASI_DMMU. */
 #define VA_DMMU_TAG_TARGET              0x0     /**< DMMU tag target register. */
 #define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */