Changeset fb28cde in mainline
- Timestamp:
- 2018-01-18T17:12:30Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8fe29a7c
- Parents:
- e7f21884
- Location:
- uspace/drv/bus/usb/xhci
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/commands.c
re7f21884 rfb28cde 546 546 TRB_SET_DEQUEUE_PTR(cmd->_header.trb, cmd->dequeue_ptr); 547 547 548 /**549 * TODO: Set DCS (see section 4.6.10).550 */551 552 548 return enqueue_command(hc, cmd); 553 549 } -
uspace/drv/bus/usb/xhci/hc.c
re7f21884 rfb28cde 477 477 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots); 478 478 479 uint64_t crcr = xhci_trb_ring_get_dequeue_ptr(&hc->cr.trb_ring); 480 if (hc->cr.trb_ring.pcs) 481 crcr |= XHCI_REG_MASK(XHCI_OP_RCS); 479 uintptr_t crcr; 480 xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr); 482 481 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr)); 483 482 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr)); -
uspace/drv/bus/usb/xhci/trb_ring.c
re7f21884 rfb28cde 272 272 } 273 273 274 void xhci_trb_ring_reset_dequeue_state(xhci_trb_ring_t *ring, uintptr_t *addr) 275 { 276 assert(ring); 277 278 ring->dequeue = trb_ring_enqueue_phys(ring); 279 280 if (addr) 281 *addr = ring->dequeue | ring->pcs; 282 } 283 274 284 /** 275 285 * Initializes an event ring. -
uspace/drv/bus/usb/xhci/trb_ring.h
re7f21884 rfb28cde 79 79 int xhci_trb_ring_enqueue_multiple(xhci_trb_ring_t *, xhci_trb_t *, size_t, uintptr_t *); 80 80 81 /** 82 * Get the initial value to fill into CRCR. 83 */ 84 static inline uintptr_t xhci_trb_ring_get_dequeue_ptr(xhci_trb_ring_t *ring) 85 { 86 return ring->dequeue; 87 } 81 void xhci_trb_ring_reset_dequeue_state(xhci_trb_ring_t *ring, uintptr_t *addr); 88 82 89 83 /** … … 94 88 ring->dequeue = phys; 95 89 } 96 97 uintptr_t xhci_trb_ring_get_dequeue_ptr(xhci_trb_ring_t *);98 90 99 91 /**
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