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00036 #ifndef __ia32_ASM_H__
00037 #define __ia32_ASM_H__
00038
00039 #include <arch/pm.h>
00040 #include <arch/types.h>
00041 #include <config.h>
00042
00043 extern __u32 interrupt_handler_size;
00044
00045 extern void paging_on(void);
00046
00047 extern void interrupt_handlers(void);
00048
00049 extern void enable_l_apic_in_msr(void);
00050
00051
00052 extern void asm_delay_loop(__u32 t);
00053 extern void asm_fake_loop(__u32 t);
00054
00055
00060 static inline void cpu_halt(void) { __asm__("hlt\n"); };
00061 static inline void cpu_sleep(void) { __asm__("hlt\n"); };
00062
00063 #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
00064 { \
00065 __native res; \
00066 __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
00067 return res; \
00068 }
00069
00070 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
00071 { \
00072 __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
00073 }
00074
00075 GEN_READ_REG(cr0);
00076 GEN_READ_REG(cr2);
00077 GEN_READ_REG(cr3);
00078 GEN_WRITE_REG(cr3);
00079
00080 GEN_READ_REG(dr0);
00081 GEN_READ_REG(dr1);
00082 GEN_READ_REG(dr2);
00083 GEN_READ_REG(dr3);
00084 GEN_READ_REG(dr6);
00085 GEN_READ_REG(dr7);
00086
00087 GEN_WRITE_REG(dr0);
00088 GEN_WRITE_REG(dr1);
00089 GEN_WRITE_REG(dr2);
00090 GEN_WRITE_REG(dr3);
00091 GEN_WRITE_REG(dr6);
00092 GEN_WRITE_REG(dr7);
00093
00101 static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
00102
00110 static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
00111
00119 static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
00120
00128 static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
00129
00137 static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
00138
00146 static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
00147
00155 static inline ipl_t interrupts_enable(void)
00156 {
00157 ipl_t v;
00158 __asm__ volatile (
00159 "pushf\n\t"
00160 "popl %0\n\t"
00161 "sti\n"
00162 : "=r" (v)
00163 );
00164 return v;
00165 }
00166
00174 static inline ipl_t interrupts_disable(void)
00175 {
00176 ipl_t v;
00177 __asm__ volatile (
00178 "pushf\n\t"
00179 "popl %0\n\t"
00180 "cli\n"
00181 : "=r" (v)
00182 );
00183 return v;
00184 }
00185
00192 static inline void interrupts_restore(ipl_t ipl)
00193 {
00194 __asm__ volatile (
00195 "pushl %0\n\t"
00196 "popf\n"
00197 : : "r" (ipl)
00198 );
00199 }
00200
00205 static inline ipl_t interrupts_read(void)
00206 {
00207 ipl_t v;
00208 __asm__ volatile (
00209 "pushf\n\t"
00210 "popl %0\n"
00211 : "=r" (v)
00212 );
00213 return v;
00214 }
00215
00222 static inline __address get_stack_base(void)
00223 {
00224 __address v;
00225
00226 __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
00227
00228 return v;
00229 }
00230
00231 static inline __u64 rdtsc(void)
00232 {
00233 __u64 v;
00234
00235 __asm__ volatile("rdtsc\n" : "=A" (v));
00236
00237 return v;
00238 }
00239
00241 static inline __address * get_ip()
00242 {
00243 __address *ip;
00244
00245 __asm__ volatile (
00246 "mov %%eip, %0"
00247 : "=r" (ip)
00248 );
00249 return ip;
00250 }
00251
00256 static inline void invlpg(__address addr)
00257 {
00258 __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
00259 }
00260
00265 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
00266 {
00267 __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
00268 }
00269
00274 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
00275 {
00276 __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
00277 }
00278
00283 static inline void idtr_load(ptr_16_32_t *idtr_reg)
00284 {
00285 __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
00286 }
00287
00292 static inline void tr_load(__u16 sel)
00293 {
00294 __asm__ volatile ("ltr %0" : : "r" (sel));
00295 }
00296
00297 #endif
00298