source: mainline/kernel/arch/arm32/src/cpu/cpu.c

Revision Log Mode:


Legend:

Added
Modified
Copied or renamed
Diff Rev Age Author Log Message
(edit) @93d8022   9 years jakub ARM cache handling fixes - boot: Use the normal outer and inner WBWA … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @d5610b9   9 years jakub Cleanup some of the cache maintenance mess on ARM - Do not define … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @9048147   10 years jakub Include fpu_context.h if necessary. lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @34847e2   11 years jano.vesely arm32: Up to 8 levels of cache are possible lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @8ff767b   11 years jano.vesely armv7+: Disable Icache on IVIVT implementation lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @8abcf4e   11 years jano.vesely armv7: Fix dcache flushing routines. lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @c8a5c8c   12 years jano.vesely arm32: Start performance counters only if we can't use timer extensions. lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Note: See TracRevisionLog for help on using the revision log.