Changeset a35b458 in mainline for kernel/arch/amd64/src/smp/ap.S
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/smp/ap.S
r3061bc1 ra35b458 55 55 xorw %ax, %ax 56 56 movw %ax, %ds 57 57 58 58 lgdtl ap_gdtr # initialize Global Descriptor Table register 59 59 60 60 movl %cr0, %eax 61 61 orl $CR0_PE, %eax … … 71 71 movw $GDT_SELECTOR(UDATA_DES), %ax 72 72 movw %ax, %gs 73 73 74 74 # Enable 64-bit page transaltion entries (CR4.PAE = 1). 75 75 # Paging is not enabled until after long mode is enabled 76 76 77 77 movl %cr4, %eax 78 78 orl $CR4_PAE, %eax 79 79 movl %eax, %cr4 80 80 81 81 leal ptl_0, %eax 82 82 movl %eax, %cr3 83 83 84 84 # Enable long mode 85 85 movl $AMD_MSR_EFER, %ecx # EFER MSR number … … 87 87 orl $AMD_LME, %eax # Set LME=1 88 88 wrmsr # Write EFER 89 89 90 90 # Enable paging to activate long mode (set CR0.PG = 1) 91 91 movl %cr0, %eax 92 92 orl $CR0_PG, %eax 93 93 movl %eax, %cr0 94 94 95 95 # At this point we are in compatibility mode 96 96 jmpl $GDT_SELECTOR(KTEXT_DES), $start64 - BOOT_OFFSET + AP_BOOT_OFFSET … … 100 100 movabsq $ctx, %rsp 101 101 movq CONTEXT_OFFSET_SP(%rsp), %rsp 102 102 103 103 pushq $0 104 104 movq %rsp, %rbp 105 105 106 106 movabsq $main_ap, %rax 107 107 callq *%rax # never returns
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