Changeset 013c4d6 in mainline for kernel/genarch/include/kbd/ns16550.h
- Timestamp:
- 2009-02-19T23:55:23Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f32d90b
- Parents:
- d1eece6
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/include/kbd/ns16550.h
rd1eece6 r013c4d6 38 38 #define KERN_NS16550_H_ 39 39 40 #include <console/chardev.h>41 40 #include <ddi/irq.h> 42 #include <ipc/irq.h>43 44 extern void ns16550_init(devno_t, uintptr_t, inr_t, cir_t, void *);45 extern void ns16550_poll(void);46 extern void ns16550_grab(void);47 extern void ns16550_release(void);48 extern char ns16550_key_read(chardev_t *);49 extern irq_ownership_t ns16550_claim(void *);50 extern void ns16550_irq_handler(irq_t *);51 52 41 #include <arch/types.h> 53 42 #include <arch/drivers/kbd.h> 54 55 /* NS16550 registers */56 #define RBR_REG 0 /** Receiver Buffer Register. */57 #define IER_REG 1 /** Interrupt Enable Register. */58 #define IIR_REG 2 /** Interrupt Ident Register (read). */59 #define FCR_REG 2 /** FIFO control register (write). */60 #define LCR_REG 3 /** Line Control register. */61 #define MCR_REG 4 /** Modem Control Register. */62 #define LSR_REG 5 /** Line Status Register. */63 43 64 44 #define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */ … … 68 48 #define MCR_OUT2 0x08 /** OUT2. */ 69 49 50 /** NS16550 registers. */ 51 struct ns16550 { 52 ioport8_t rbr; /**< Receiver Buffer Register. */ 53 ioport8_t ier; /**< Interrupt Enable Register. */ 54 union { 55 ioport8_t iir; /**< Interrupt Ident Register (read). */ 56 ioport8_t fcr; /**< FIFO control register (write). */ 57 } __attribute__ ((packed)); 58 ioport8_t lcr; /**< Line Control register. */ 59 ioport8_t mcr; /**< Modem Control Register. */ 60 ioport8_t lsr; /**< Line Status Register. */ 61 } __attribute__ ((packed)); 62 typedef struct ns16550 ns16550_t; 63 70 64 /** Structure representing the ns16550 device. */ 71 typedef struct {65 typedef struct ns16550_instance { 72 66 devno_t devno; 73 /** Memory mapped registers of the ns16550. */74 volatile ioport_t io_port;75 } ns16550_ t;67 ns16550_t *ns16550; 68 irq_t *irq; 69 } ns16550_instance_t; 76 70 77 static inline uint8_t ns16550_rbr_read(ns16550_t *dev) 78 { 79 return pio_read_8(dev->io_port + RBR_REG); 80 } 81 static inline void ns16550_rbr_write(ns16550_t *dev, uint8_t v) 82 { 83 pio_write_8(dev->io_port + RBR_REG, v); 84 } 85 86 static inline uint8_t ns16550_ier_read(ns16550_t *dev) 87 { 88 return pio_read_8(dev->io_port + IER_REG); 89 } 90 91 static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v) 92 { 93 pio_write_8(dev->io_port + IER_REG, v); 94 } 95 96 static inline uint8_t ns16550_iir_read(ns16550_t *dev) 97 { 98 return pio_read_8(dev->io_port + IIR_REG); 99 } 100 101 static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v) 102 { 103 pio_write_8(dev->io_port + FCR_REG, v); 104 } 105 106 static inline uint8_t ns16550_lcr_read(ns16550_t *dev) 107 { 108 return pio_read_8(dev->io_port + LCR_REG); 109 } 110 111 static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v) 112 { 113 pio_write_8(dev->io_port + LCR_REG, v); 114 } 115 116 static inline uint8_t ns16550_lsr_read(ns16550_t *dev) 117 { 118 return pio_read_8(dev->io_port + LSR_REG); 119 } 120 121 static inline uint8_t ns16550_mcr_read(ns16550_t *dev) 122 { 123 return pio_read_8(dev->io_port + MCR_REG); 124 } 125 126 static inline void ns16550_mcr_write(ns16550_t *dev, uint8_t v) 127 { 128 pio_write_8(dev->io_port + MCR_REG, v); 129 } 71 extern bool ns16550_init(ns16550_t *, devno_t, inr_t, cir_t, void *); 72 extern void ns16550_grab(void); 73 extern void ns16550_release(void); 74 extern irq_ownership_t ns16550_claim(void *); 75 extern void ns16550_irq_handler(irq_t *); 130 76 131 77 #endif
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