Changeset 0c40fd5 in mainline

Timestamp:

2013-08-07T18:38:44Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ae5fb7c8

Parents:

8ff767b

Message:

arm32: Fix pagetables in cacheable memory.

Set memory attributes in TTBR0/1

Location:

kernel/arch/arm32/include/arch

Files:

• cp15.h (modified) (1 diff)
• mm/page.h (modified) (1 diff)
• mm/page_armv4.h (modified) (1 diff)
• mm/page_armv6.h (modified) (2 diffs)

kernel/arch/arm32/include/arch/cp15.h

@@ -301 +301 @@
 
 /* Memory protection and control registers */
+enum {
+        TTBR_ADDR_MASK = 0xffffff80,
+        TTBR_NOS_FLAG = 1 << 5,
+        TTBR_RGN_MASK = 0x3 << 3,
+        TTBR_RGN_NO_CACHE = 0x0 << 3,
+        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
+        TTBR_RGN_WT_CACHE = 0x2 << 3,
+        TTBR_RGN_WB_CACHE = 0x3 << 3,
+        TTBR_S_FLAG = 1 << 1,
+        TTBR_C_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);

kernel/arch/arm32/include/arch/mm/page.h

@@ -145 +145 @@
  * @param pt Pointer to the page table to set.
  *
+ * Page tables are always in cacheable memory.
+ * Make sure the memory type is correct.
  */
 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
 {
-        TTBR0_write((uint32_t)pt);
+        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
+        val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+        TTBR0_write(val);
 }
 

kernel/arch/arm32/include/arch/mm/page_armv4.h

@@ -120 +120 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE       2
 
-#define pt_coherence_m(page, count)
+#define pt_coherence_m(pt, count) \
+do { \
+        for (unsigned i = 0; i < count; ++i) \
+                DCCMVAU_write((uintptr_t)(pt + i)); \
+        read_barrier(); \
+} while (0)
 
 /** Returns level 0 page table entry flags.

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -151 +151 @@
  *
  * ARM Architecture reference chp. B3.10.1 p. B3-1375
- */
-//TODO: DCCMVAU does not work.
+ * @note: see TTRB0/1 for pt memory type
+ */
 #define pt_coherence_m(pt, count) \
 do { \
         for (unsigned i = 0; i < count; ++i) \
-                DCCMVAC_write((uintptr_t)(pt + i)); \
+                DCCMVAU_write((uintptr_t)(pt + i)); \
         read_barrier(); \
 } while (0)
@@ -300 +300 @@
         p->should_be_zero_0 = 0;
         p->should_be_zero_1 = 0;
-        write_barrier();
         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
         pt_coherence(p);