Changeset ae5fb7c8 in mainline

Timestamp:

2013-08-07T21:02:08Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

15187c3

Parents:

0c40fd5

Message:

arm32: Set proper memory type in boot pt.

Add explanatory comments.

Files:

• boot/arch/arm32/src/mm.c (modified) (2 diffs)
• kernel/arch/arm32/include/arch/mm/page.h (modified) (1 diff)
• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -141 +141 @@
         pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
 #ifdef PROCESSOR_ARCH_armv7_a
+        /*
+         * Keeps this setting in sync with memory type attributes in:
+         * init_boot_pt (boot/arch/arm32/src/mm.c)
+         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
+         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
+         */
         //TODO: Use write-back write-allocate caches
         pte->tex = section_cacheable(frame) ? 6 : 0;
@@ -161 +167 @@
 static void init_boot_pt(void)
 {
-        const pfn_t split_page = PTL0_ENTRIES;
-        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
-        pfn_t page;
-        for (page = 0; page < split_page; page++)
+        /*
+         * Create 1:1 virtual-physical mapping.
+         * Physical memory on BBxM a BBone starts at 2GB
+         * boundary, gta02 has a memory mirror at 2GB.
+         * icp somehow works (probably due to limited address size)
+         */
+        for (pfn_t page = 0; page < PTL0_ENTRIES; page++)
                 init_ptl0_section(&boot_pt[page], page);
-        
-        asm volatile (
-                "mcr p15, 0, %[pt], c2, c0, 0\n"
-                :: [pt] "r" (boot_pt)
-        );
+
+        /*
+         * Tell MMU page might be cached. Keeps this setting in sync
+         * with memory type attributes in:
+         * init_ptl0_section (boot/arch/arm32/src/mm.c)
+         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
+         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
+         */
+        uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
+        val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+        TTBR0_write(val);
 }
 

kernel/arch/arm32/include/arch/mm/page.h

@@ -146 +146 @@
  *
  * Page tables are always in cacheable memory.
- * Make sure the memory type is correct.
+ * Make sure the memory type is correct, and in sync with:
+ * init_boot_pt (boot/arch/arm32/src/mm.c)
+ * init_ptl0_section (boot/arch/arm32/src/mm.c)
+ * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
  */
 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -260 +260 @@
                  * Write-through, no write-allocate memory, see ch. B3.8.2
                  * (p. B3-1358) of ARM Architecture reference manual.
+                 * Make sure the memory type is correct, and in sync with:
+                 * init_boot_pt (boot/arch/arm32/src/mm.c)
+                 * init_ptl0_section (boot/arch/arm32/src/mm.c)
+                 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
                  */
                 //TODO: Use writeback, write-allocate caches