Changeset 13927cf in mainline for uspace/drv/ehci-hcd/pci.c


Ignore:
Timestamp:
2011-03-07T14:30:32Z (14 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
275bf456
Parents:
bcaefe3
Message:

Doxygen and other comments

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/ehci-hcd/pci.c

    rbcaefe3 r13927cf  
    4848
    4949#define PAGE_SIZE_MASK 0xfffff000
     50
    5051#define HCC_PARAMS_OFFSET 0x8
    5152#define HCC_PARAMS_EECP_MASK 0xff
     
    6263#define WAIT_STEP 10
    6364
    64 
    6565/** Get address of registers and IRQ for given device.
    6666 *
    6767 * @param[in] dev Device asking for the addresses.
    68  * @param[out] io_reg_address Base address of the I/O range.
    69  * @param[out] io_reg_size Size of the I/O range.
     68 * @param[out] mem_reg_address Base address of the memory range.
     69 * @param[out] mem_reg_size Size of the memory range.
    7070 * @param[out] irq_no IRQ assigned to the device.
    7171 * @return Error code.
     
    136136}
    137137/*----------------------------------------------------------------------------*/
     138/** Calls the PCI driver with a request to enable interrupts
     139 *
     140 * @param[in] device Device asking for interrupts
     141 * @return Error code.
     142 */
    138143int pci_enable_interrupts(ddf_dev_t *device)
    139144{
     
    148153}
    149154/*----------------------------------------------------------------------------*/
     155/** Implements BIOS handoff routine as decribed in EHCI spec
     156 *
     157 * @param[in] device Device asking for interrupts
     158 * @return Error code.
     159 */
    150160int pci_disable_legacy(ddf_dev_t *device)
    151161{
     
    165175
    166176
    167         /* read register space BAR */
     177        /* read register space BASE BAR */
    168178        sysarg_t address = 0x10;
    169179        sysarg_t value;
     
    175185        usb_log_info("Register space BAR at %p:%x.\n", address, value);
    176186
    177         /* clear lower byte, it's not part of the address */
     187        /* clear lower byte, it's not part of the BASE address */
    178188        uintptr_t registers = (value & 0xffffff00);
    179         usb_log_info("Memory registers address:%p.\n", registers);
    180 
    181         /* if nothing setup the hc, the we don't need to to turn it off */
     189        usb_log_info("Memory registers BASE address:%p.\n", registers);
     190
     191        /* if nothing setup the hc, we don't need to turn it off */
    182192        if (registers == 0)
    183193                return ENOTSUP;
     
    195205        const uint32_t hcc_params =
    196206            *(uint32_t*)(registers + HCC_PARAMS_OFFSET);
    197 
    198207        usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
     208
     209        /* Read value of EHCI Extended Capabilities Pointer
     210         * (points to PCI config space) */
    199211        uint32_t eecp =
    200212            (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
    201213        usb_log_debug("Value of EECP: %x.\n", eecp);
    202214
     215        /* Read the second EEC. i.e. Legacy Support and Control register */
     216        /* TODO: Check capability type here */
    203217        ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
    204218            IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
     
    206220        usb_log_debug("USBLEGCTLSTS: %x.\n", value);
    207221
     222        /* Read the first EEC. i.e. Legacy Support register */
     223        /* TODO: Check capability type here */
    208224        ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
    209225            IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
     
    211227        usb_log_debug2("USBLEGSUP: %x.\n", value);
    212228
    213         /* request control from firmware/BIOS, by writing 1 to highest byte */
     229        /* Request control from firmware/BIOS, by writing 1 to highest byte.
     230         * (OS Control semaphore)*/
    214231        ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
    215232           IPC_M_CONFIG_SPACE_WRITE_8, eecp + USBLEGSUP_OFFSET + 3, 1);
    216         CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) request OS EHCI control.\n",
     233        CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to request OS EHCI control.\n",
    217234            ret);
    218235
    219236        size_t wait = 0;
    220         /* wait for BIOS to release control */
     237        /* Wait for BIOS to release control. */
    221238        while ((wait < DEFAULT_WAIT) && (value & USBLEGSUP_BIOS_CONTROL)) {
    222239                async_usleep(WAIT_STEP);
     
    226243        }
    227244
     245
    228246        if ((value & USBLEGSUP_BIOS_CONTROL) != 0) {
    229247                usb_log_info("BIOS released control after %d usec.\n", wait);
    230248        } else {
     249                /* BIOS failed to hand over control, this should not happen. */
    231250                usb_log_warning( "BIOS failed to release control after"
    232251                    "%d usecs, force it.\n", wait);
     
    236255                CHECK_RET_HANGUP_RETURN(ret,
    237256                    "Failed(%d) to force OS EHCI control.\n", ret);
    238         }
    239 
    240 
    241         /* zero SMI enables in legacy control register */
     257                /* TODO: This does not seem to work on my machine */
     258        }
     259
     260
     261        /* Zero SMI enables in legacy control register.
     262         * It would prevent pre-OS code from interfering. */
    242263        ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
    243264           IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET, 0);
     
    245266        usb_log_debug("Zeroed USBLEGCTLSTS register.\n");
    246267
     268        /* Read again Legacy Support and Control register */
    247269        ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
    248270            IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
     
    250272        usb_log_debug2("USBLEGCTLSTS: %x.\n", value);
    251273
     274        /* Read again Legacy Support register */
    252275        ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
    253276            IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
     
    259282 */
    260283
    261         /* size of capability registers in memory space */
     284        /* Get size of capability registers in memory space. */
    262285        uint8_t operation_offset = *(uint8_t*)registers;
    263286        usb_log_debug("USBCMD offset: %d.\n", operation_offset);
    264         /* zero USBCMD register */
     287
     288        /* Zero USBCMD register. */
    265289        volatile uint32_t *usbcmd =
    266290         (uint32_t*)((uint8_t*)registers + operation_offset);
     
    273297        }
    274298
    275 
    276299        async_hangup(parent_phone);
    277300        return ret;
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