Changeset 13927cf in mainline for uspace/drv/ehci-hcd/pci.c
- Timestamp:
- 2011-03-07T14:30:32Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 275bf456
- Parents:
- bcaefe3
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/ehci-hcd/pci.c
rbcaefe3 r13927cf 48 48 49 49 #define PAGE_SIZE_MASK 0xfffff000 50 50 51 #define HCC_PARAMS_OFFSET 0x8 51 52 #define HCC_PARAMS_EECP_MASK 0xff … … 62 63 #define WAIT_STEP 10 63 64 64 65 65 /** Get address of registers and IRQ for given device. 66 66 * 67 67 * @param[in] dev Device asking for the addresses. 68 * @param[out] io_reg_address Base address of the I/Orange.69 * @param[out] io_reg_size Size of the I/Orange.68 * @param[out] mem_reg_address Base address of the memory range. 69 * @param[out] mem_reg_size Size of the memory range. 70 70 * @param[out] irq_no IRQ assigned to the device. 71 71 * @return Error code. … … 136 136 } 137 137 /*----------------------------------------------------------------------------*/ 138 /** Calls the PCI driver with a request to enable interrupts 139 * 140 * @param[in] device Device asking for interrupts 141 * @return Error code. 142 */ 138 143 int pci_enable_interrupts(ddf_dev_t *device) 139 144 { … … 148 153 } 149 154 /*----------------------------------------------------------------------------*/ 155 /** Implements BIOS handoff routine as decribed in EHCI spec 156 * 157 * @param[in] device Device asking for interrupts 158 * @return Error code. 159 */ 150 160 int pci_disable_legacy(ddf_dev_t *device) 151 161 { … … 165 175 166 176 167 /* read register space BA R */177 /* read register space BASE BAR */ 168 178 sysarg_t address = 0x10; 169 179 sysarg_t value; … … 175 185 usb_log_info("Register space BAR at %p:%x.\n", address, value); 176 186 177 /* clear lower byte, it's not part of the address */187 /* clear lower byte, it's not part of the BASE address */ 178 188 uintptr_t registers = (value & 0xffffff00); 179 usb_log_info("Memory registers address:%p.\n", registers);180 181 /* if nothing setup the hc, the we don't need toto turn it off */189 usb_log_info("Memory registers BASE address:%p.\n", registers); 190 191 /* if nothing setup the hc, we don't need to turn it off */ 182 192 if (registers == 0) 183 193 return ENOTSUP; … … 195 205 const uint32_t hcc_params = 196 206 *(uint32_t*)(registers + HCC_PARAMS_OFFSET); 197 198 207 usb_log_debug("Value of hcc params register: %x.\n", hcc_params); 208 209 /* Read value of EHCI Extended Capabilities Pointer 210 * (points to PCI config space) */ 199 211 uint32_t eecp = 200 212 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK; 201 213 usb_log_debug("Value of EECP: %x.\n", eecp); 202 214 215 /* Read the second EEC. i.e. Legacy Support and Control register */ 216 /* TODO: Check capability type here */ 203 217 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), 204 218 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value); … … 206 220 usb_log_debug("USBLEGCTLSTS: %x.\n", value); 207 221 222 /* Read the first EEC. i.e. Legacy Support register */ 223 /* TODO: Check capability type here */ 208 224 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), 209 225 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value); … … 211 227 usb_log_debug2("USBLEGSUP: %x.\n", value); 212 228 213 /* request control from firmware/BIOS, by writing 1 to highest byte */ 229 /* Request control from firmware/BIOS, by writing 1 to highest byte. 230 * (OS Control semaphore)*/ 214 231 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), 215 232 IPC_M_CONFIG_SPACE_WRITE_8, eecp + USBLEGSUP_OFFSET + 3, 1); 216 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) request OS EHCI control.\n",233 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to request OS EHCI control.\n", 217 234 ret); 218 235 219 236 size_t wait = 0; 220 /* wait for BIOS to release control*/237 /* Wait for BIOS to release control. */ 221 238 while ((wait < DEFAULT_WAIT) && (value & USBLEGSUP_BIOS_CONTROL)) { 222 239 async_usleep(WAIT_STEP); … … 226 243 } 227 244 245 228 246 if ((value & USBLEGSUP_BIOS_CONTROL) != 0) { 229 247 usb_log_info("BIOS released control after %d usec.\n", wait); 230 248 } else { 249 /* BIOS failed to hand over control, this should not happen. */ 231 250 usb_log_warning( "BIOS failed to release control after" 232 251 "%d usecs, force it.\n", wait); … … 236 255 CHECK_RET_HANGUP_RETURN(ret, 237 256 "Failed(%d) to force OS EHCI control.\n", ret); 238 } 239 240 241 /* zero SMI enables in legacy control register */ 257 /* TODO: This does not seem to work on my machine */ 258 } 259 260 261 /* Zero SMI enables in legacy control register. 262 * It would prevent pre-OS code from interfering. */ 242 263 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), 243 264 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET, 0); … … 245 266 usb_log_debug("Zeroed USBLEGCTLSTS register.\n"); 246 267 268 /* Read again Legacy Support and Control register */ 247 269 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), 248 270 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value); … … 250 272 usb_log_debug2("USBLEGCTLSTS: %x.\n", value); 251 273 274 /* Read again Legacy Support register */ 252 275 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), 253 276 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value); … … 259 282 */ 260 283 261 /* size of capability registers in memory space*/284 /* Get size of capability registers in memory space. */ 262 285 uint8_t operation_offset = *(uint8_t*)registers; 263 286 usb_log_debug("USBCMD offset: %d.\n", operation_offset); 264 /* zero USBCMD register */ 287 288 /* Zero USBCMD register. */ 265 289 volatile uint32_t *usbcmd = 266 290 (uint32_t*)((uint8_t*)registers + operation_offset); … … 273 297 } 274 298 275 276 299 async_hangup(parent_phone); 277 300 return ret;
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