Changeset 20d50a1 in mainline for doc/mm

Timestamp:

2006-01-13T13:02:45Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f9425006

Parents:

0369911

Message:

Memory management work.

• vm.* → as.* (as like address space is, imho, more fitting)
• Don't do TLB shootdown on vm_install(). Some architectures only need to call tlb_invalidate_asid().
• Don't allocate all frames for as_area in as_area_create(), but let them be allocated on-demand by as_page_fault().
• Add high-level page fault handler as_page_fault().
• Add as_area_load_mapping().

File:

• doc/mm (modified) (2 diffs)

doc/mm

@@ -2 +2 @@
 =================
 
-SPARTAN kernel deploys generic interface for 4-level page tables,
-no matter what the real underlying hardware architecture is.
+1. Virtual Address Translation
+
+1.1 Hierarchical 4-level per address space page tables
+
+SPARTAN kernel deploys generic interface for 4-level page tables
+for these architectures: amd64, ia32, mips32 and ppc32. In this
+setting, page tables are hierarchical and are not shared by
+address spaces (i.e. one set of page tables per address space).
 
 
@@ -51 +57 @@
 left out. TLB-only architectures are to define custom format for software page
 tables.
+
+
+
+1.2 Single global page hash table
+
+Generic page hash table interface is deployed on 64-bit architectures without
+implied hardware support for hierarchical page tables, i.e. ia64 and sparc64.
+There is only one global page hash table in the system shared by all address
+spaces.