Changeset 23b7c02 in mainline for kernel/arch/arm32/include/arch/cp15.h

Timestamp:

2013-09-04T06:58:57Z (12 years ago)

Author:

Manuele Conti <conti.ma@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7664469

Parents:

caf5382 (diff), aa2a049 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge with Mainline changes.

File:

• kernel/arch/arm32/include/arch/cp15.h (modified) (5 diffs)

kernel/arch/arm32/include/arch/cp15.h

@@ -171 +171 @@
         CCSIDR_LINESIZE_MASK = 0x7,
         CCSIDR_LINESIZE_SHIFT = 0,
+#define CCSIDR_SETS(val) \
+        (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
+#define CCSIDR_WAYS(val) \
+        (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
+/* The register value is log(linesize_in_words) - 2 */
+#define CCSIDR_LINESIZE_LOG(val) \
+        (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
 };
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
@@ -187 +194 @@
         CLIDR_UNI_CACHE = 0x4,
         CLIDR_CACHE_MASK = 0x7,
-#define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
+/** levels counted from 0 */
+#define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
 };
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
@@ -293 +301 @@
 
 /* Memory protection and control registers */
+enum {
+        TTBR_ADDR_MASK = 0xffffff80,
+        TTBR_NOS_FLAG = 1 << 5,
+        TTBR_RGN_MASK = 0x3 << 3,
+        TTBR_RGN_NO_CACHE = 0x0 << 3,
+        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
+        TTBR_RGN_WT_CACHE = 0x2 << 3,
+        TTBR_RGN_WB_CACHE = 0x3 << 3,
+        TTBR_S_FLAG = 1 << 1,
+        TTBR_C_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
@@ -363 +382 @@
 
 CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
-CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2);
+CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
 
 CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
@@ -369 +388 @@
 CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
 CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
-CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4);
-CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5);
-CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6);
-CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7);
+CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
+CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
+CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
+CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);