Changeset 2a77eaa2 in mainline for boot/arch/arm32/include/mm.h

Timestamp:

2013-01-01T18:17:05Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f65b8e0c

Parents:

e55fcd2

Message:

arm32, boot: Drop l2 cache enabling. Add armv7 cache invalidate.

L2 Cache on CortexA8 is enabled by default, we can control it together with L1 data cache using C bit in sctlr.

(No files)