Changeset 2a8f38a in mainline
- Timestamp:
- 2013-01-03T20:46:36Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9b6e40b
- Parents:
- f65b8e0c
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/include/barrier.h
rf65b8e0c r2a8f38a 43 43 #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") 44 44 45 #if defined PROCESSOR_ARCH_armv7_a 46 /* ARMv7 uses instructions for memory barriers see ARM Architecture reference 47 * manual for details: 48 * DMB: ch. A8.8.43 page A8-376 49 * DSB: ch. A8.8.44 page A8-378 50 * See ch. A3.8.3 page A3-148 for details about memory barrier implementation 51 * and functionality on armv7 architecture. 52 */ 53 #define memory_barrier() asm volatile ("dmb" ::: "memory") 54 #define read_barrier() asm volatile ("dsb" ::: "memory") 55 #define write_barrier() asm volatile ("dsb st" ::: "memory") 56 #elif defined PROCESSOR_ARCH_armv6 57 /* ARMv6- use system control coprocessor (CP15) for memory barrier instructions. 58 * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs, 59 * CP15 implementation is mandatory only for armv6+. 60 */ 61 #define memory_barrier() asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 5" ::: "r0", "memory") 62 #define read_barrier() asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 4" ::: "r0", "memory") 63 #define write_barrier() read_barrier() 64 #else 65 /* Older manuals mention syscalls as a way to implement cache coherency and 66 * barriers. See for example ARM Architecture Reference Manual Version D 67 * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28) 68 */ 69 // TODO implement on per PROCESSOR basis 45 70 #define memory_barrier() asm volatile ("" ::: "memory") 46 71 #define read_barrier() asm volatile ("" ::: "memory") 47 72 #define write_barrier() asm volatile ("" ::: "memory") 73 #endif 48 74 49 75 /*
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