Changeset 2b0db98 in mainline for uspace/srv/bd/ata_bd/ata_bd.h


Ignore:
Timestamp:
2011-01-07T14:02:56Z (14 years ago)
Author:
Lubos Slovak <lubos.slovak@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6986418
Parents:
d99120f (diff), 0f191a2 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merged development into lelian/hidd

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/srv/bd/ata_bd/ata_bd.h

    rd99120f r2b0db98  
    3030 * @{
    3131 */
    32 /** @file
     32/** @file ATA driver definitions.
    3333 */
    3434
     
    4040#include <str.h>
    4141
    42 enum {
    43         CTL_READ_START  = 0,
    44         CTL_WRITE_START = 1,
    45 };
    46 
    47 enum {
    48         STATUS_FAILURE = 0
    49 };
    50 
    51 enum {
    52         MAX_DISKS       = 2
    53 };
    54 
    55 /** ATA Command Register Block. */
    56 typedef union {
    57         /* Read/Write */
    58         struct {
    59                 uint16_t data_port;
    60                 uint8_t sector_count;
    61                 uint8_t sector_number;
    62                 uint8_t cylinder_low;
    63                 uint8_t cylinder_high;
    64                 uint8_t drive_head;
    65                 uint8_t pad_rw0;               
    66         };
    67 
    68         /* Read Only */
    69         struct {
    70                 uint8_t pad_ro0;
    71                 uint8_t error;
    72                 uint8_t pad_ro1[5];
    73                 uint8_t status;
    74         };
    75 
    76         /* Write Only */
    77         struct {
    78                 uint8_t pad_wo0;
    79                 uint8_t features;
    80                 uint8_t pad_wo1[5];
    81                 uint8_t command;
    82         };
    83 } ata_cmd_t;
    84 
    85 typedef union {
    86         /* Read */
    87         struct {
    88                 uint8_t pad0[6];
    89                 uint8_t alt_status;
    90                 uint8_t drive_address;
    91         };
    92 
    93         /* Write */
    94         struct {
    95                 uint8_t pad1[6];
    96                 uint8_t device_control;
    97                 uint8_t pad2;
    98         };
    99 } ata_ctl_t;
    100 
    101 enum devctl_bits {
    102         DCR_SRST        = 0x04, /**< Software Reset */
    103         DCR_nIEN        = 0x02  /**< Interrupt Enable (negated) */
    104 };
    105 
    106 enum status_bits {
    107         SR_BSY          = 0x80, /**< Busy */
    108         SR_DRDY         = 0x40, /**< Drive Ready */
    109         SR_DWF          = 0x20, /**< Drive Write Fault */
    110         SR_DSC          = 0x10, /**< Drive Seek Complete */
    111         SR_DRQ          = 0x08, /**< Data Request */
    112         SR_CORR         = 0x04, /**< Corrected Data */
    113         SR_IDX          = 0x02, /**< Index */
    114         SR_ERR          = 0x01  /**< Error */
    115 };
    116 
    117 enum drive_head_bits {
    118         DHR_LBA         = 0x40, /**< Use LBA addressing mode */
    119         DHR_DRV         = 0x10  /**< Select device 1 */
    120 };
    121 
    122 enum error_bits {
    123         ER_BBK          = 0x80, /**< Bad Block Detected */
    124         ER_UNC          = 0x40, /**< Uncorrectable Data Error */
    125         ER_MC           = 0x20, /**< Media Changed */
    126         ER_IDNF         = 0x10, /**< ID Not Found */
    127         ER_MCR          = 0x08, /**< Media Change Request */
    128         ER_ABRT         = 0x04, /**< Aborted Command */
    129         ER_TK0NF        = 0x02, /**< Track 0 Not Found */
    130         ER_AMNF         = 0x01  /**< Address Mark Not Found */
    131 };
    132 
    133 enum ata_command {
    134         CMD_READ_SECTORS        = 0x20,
    135         CMD_READ_SECTORS_EXT    = 0x24,
    136         CMD_WRITE_SECTORS       = 0x30,
    137         CMD_WRITE_SECTORS_EXT   = 0x34,
    138         CMD_IDENTIFY_DRIVE      = 0xEC
    139 };
     42/** Base addresses for ATA I/O blocks. */
     43typedef struct {
     44        uintptr_t cmd;  /**< Command block base address. */
     45        uintptr_t ctl;  /**< Control block base address. */
     46} ata_base_t;
    14047
    14148/** Timeout definitions. Unit is 10 ms. */
     
    14451        TIMEOUT_BSY     =  100, /*  1 s */
    14552        TIMEOUT_DRDY    = 1000  /* 10 s */
    146 };
    147 
    148 /** Data returned from @c identify command. */
    149 typedef struct {
    150         uint16_t gen_conf;
    151         uint16_t cylinders;
    152         uint16_t _res2;
    153         uint16_t heads;
    154         uint16_t _vs4;
    155         uint16_t _vs5;
    156         uint16_t sectors;
    157         uint16_t _vs7;
    158         uint16_t _vs8;
    159         uint16_t _vs9;
    160 
    161         uint16_t serial_number[10];
    162         uint16_t _vs20;
    163         uint16_t _vs21;
    164         uint16_t vs_bytes;
    165         uint16_t firmware_rev[4];
    166         uint16_t model_name[20];
    167 
    168         uint16_t max_rw_multiple;
    169         uint16_t _res48;
    170         uint16_t caps;
    171         uint16_t _res50;
    172         uint16_t pio_timing;
    173         uint16_t dma_timing;
    174 
    175         uint16_t validity;
    176         uint16_t cur_cyl;
    177         uint16_t cur_heads;
    178         uint16_t cur_sectors;
    179         uint16_t cur_capacity0;
    180         uint16_t cur_capacity1;
    181         uint16_t mss;
    182         uint16_t total_lba28_0;
    183         uint16_t total_lba28_1;
    184         uint16_t sw_dma;
    185         uint16_t mw_dma;
    186         uint16_t pio_modes;
    187         uint16_t min_mw_dma_cycle;
    188         uint16_t rec_mw_dma_cycle;
    189         uint16_t min_raw_pio_cycle;
    190         uint16_t min_iordy_pio_cycle;
    191 
    192         uint16_t _res69;
    193         uint16_t _res70;
    194         uint16_t _res71;
    195         uint16_t _res72;
    196         uint16_t _res73;
    197         uint16_t _res74;
    198 
    199         uint16_t queue_depth;
    200         uint16_t _res76[1 + 79 - 76];
    201         uint16_t version_maj;
    202         uint16_t version_min;
    203         uint16_t cmd_set0;
    204         uint16_t cmd_set1;
    205         uint16_t csf_sup_ext;
    206         uint16_t csf_enabled0;
    207         uint16_t csf_enabled1;
    208         uint16_t csf_default;
    209         uint16_t udma;
    210 
    211         uint16_t _res89[1 + 99 - 89];
    212 
    213         /* Total number of blocks in LBA-48 addressing */
    214         uint16_t total_lba48_0;
    215         uint16_t total_lba48_1;
    216         uint16_t total_lba48_2;
    217         uint16_t total_lba48_3;
    218 
    219         /* Note: more fields are defined in ATA/ATAPI-7 */
    220         uint16_t _res104[1 + 127 - 104];
    221         uint16_t _vs128[1 + 159 - 128];
    222         uint16_t _res160[1 + 255 - 160];
    223 } identify_data_t;
    224 
    225 enum ata_caps {
    226         cap_iordy       = 0x0800,
    227         cap_iordy_cbd   = 0x0400,
    228         cap_lba         = 0x0200,
    229         cap_dma         = 0x0100
    230 };
    231 
    232 /** Bits of @c identify_data_t.cmd_set1 */
    233 enum ata_cs1 {
    234         cs1_addr48      = 0x0400        /**< 48-bit address feature set */
    23553};
    23654
     
    26987} block_coord_t;
    27088
     89/** ATA device state structure. */
    27190typedef struct {
    27291        bool present;
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