Changeset 32fffef0 in mainline for kernel/arch/sparc64/include/barrier.h
- Timestamp:
- 2006-08-29T11:06:57Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0fa6044
- Parents:
- c8ea4a8b
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/barrier.h
rc8ea4a8b r32fffef0 52 52 * The FLUSH instruction takes address parameter. 53 53 * As such, it may trap if the address is not found in DTLB. 54 * However, JPS1 implementations are free to ignore the trap. 54 * 55 * The entire kernel text is mapped by a locked ITLB and 56 * DTLB entries. Therefore, when this function is called, 57 * the %o7 register will always be in the range mapped by 58 * DTLB. 55 59 */ 56 60 57 __asm__ volatile ("flush % 0\n" :: "r" (0x400000));61 __asm__ volatile ("flush %o7\n"); 58 62 } 59 63
Note:
See TracChangeset
for help on using the changeset viewer.