Changeset 44d0758 in mainline for kernel/arch/sparc64/src/start.S

Timestamp:

2006-11-22T18:35:17Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

aca95f6b

Parents:

eb353b3

Message:

Add option to compile the sparc64 kernel without the TTE_CV bit support.
The bit is not used by default now.
Enabling it may theoretically lead to physical memory inconsistencies until code that
mitigates the problem is written.

File:

• kernel/arch/sparc64/src/start.S (modified) (2 diffs)

kernel/arch/sparc64/src/start.S

@@ -123 +123 @@
         membar #Sync
 
+#ifdef CONFIG_VIRT_IDX_CACHE
+#define TTE_LOW_DATA(imm)       (TTE_CP | TTE_CV | TTE_P | LMA | (imm))
+#else /* CONFIG_VIRT_IDX_CACHE */
+#define TTE_LOW_DATA(imm)       (TTE_CP | TTE_P | LMA | (imm))
+#endif /* CONFIG_VIRT_IDX_CACHE */
+
 #define SET_TLB_DATA(r1, r2, imm) \
-        set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
+        set TTE_LOW_DATA(imm), %r1; \
         or %r1, %l5, %r1; \
         mov PAGESIZE_4M, %r2; \
@@ -349 +355 @@
 .global kernel_8k_tlb_data_template
 kernel_8k_tlb_data_template:
-        .quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W)
+#ifdef CONFIG_VIRT_IDX_CACHE
+        .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_CV | TTE_P | TTE_W)
+#else /* CONFIG_VIRT_IDX_CACHE */
+        .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_P | TTE_W)
+#endif /* CONFIG_VIRT_IDX_CACHE */