Changeset 46a6a5d in mainline for kernel/arch/arm32/include/mm/page.h

Timestamp:

2012-12-30T21:17:39Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a4afc8d

Parents:

876160ca

Message:

arm32: Reorganize CPU initialization.

Extensions that have safe fallback/ignore mechanism can be enabled on all CPUs.
Access alignment and data cache coherency is defined for armv6 and armv7.
ICache coherency is implementation defined, enable only for cortex-a8.

(No files)